AT89C51CC03CA-7CTUM ATMEL [ATMEL Corporation], AT89C51CC03CA-7CTUM Datasheet
AT89C51CC03CA-7CTUM
Manufacturer Part Number
AT89C51CC03CA-7CTUM
Description
Enhanced 8-bit MCU with CAN Controller and Flash Memory
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
1.AT89C51CC03CA-7CTUM.pdf
(197 pages)
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Features
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1.
80C51 Core Architecture
256 Bytes of On-chip RAM
2048 Bytes of On-chip ERAM
64K Bytes of On-chip Flash Memory
2K Bytes of On-chip Flash for Bootloader
2K Bytes of On-chip EEPROM
Read/Write Cycle: 100K
Integrated Power Monitor (POR: PFD) To Supervise Internal Power Supply
14-sources 4-level Interrupts
Three 16-bit Timers/Counters
Full Duplex UART Compatible 80C51
High-speed Architecture
Five Ports: 32 + 4 Digital I/O Lines
Five-channel 16-bit PCA with
Double Data Pointer
21-bit WatchDog Timer (7 Programmable Bits)
A 10-bit Resolution Analog to Digital Converter (ADC) with 8 Multiplexed Inputs
SPI Interface, (PLCC52, VPFP64 and CABGA 64 packages only)
Full CAN Controller
– Data Retention: 10 Years at 85°C
– Read/Write Cycle: 100K
– In Standard Mode:
– In X2 mode (6 Clocks/machine cycle)
– PWM (8-bit)
– High-speed Output
– Timer and Edge Capture
– Fully Compliant with CAN Rev 2.0A and 2.0B
– Optimized Structure for Communication Management (Via SFR)
– 15 Independent Message Objects
– Supports
– 1-Mbit/s Maximum Transfer Rate at 8 MHz
– Readable Error Counters
– Programmable Link to On-chip Timer for Time Stamping and Network
– Independent Baud Rate Prescaler
– Data, Remote, Error and Overload Frame Handling
Synchronization
At BRP = 1 sampling point will be fixed.
40 MHz (Vcc 3V to 5.5V, both Internal and external code execution)
60 MHz (Vcc 4.5V to 5.5V and Internal Code execution only)
20 MHz (Vcc 3V to 5.5V, both Internal and external code execution)
30 MHz (Vcc 4.5V to 5.5V and Internal Code execution only)
– Each Message Object Programmable on Transmission or Reception
– Individual Tag and Mask Filters up to 29-bit Identifier/Channel
– 8-byte Cyclic Data Register (FIFO)/Message Object
– 16-bit Status and Control Register/Message Object
– 16-bit Time-Stamping Register/Message Object
– CAN Specification 2.0 Part A or 2.0 Part B Programmable for Each Message
Object
– Access to Message Object Control and Data Registers Via SFR
– Programmable Reception Buffer Length Up To 15 Message Objects
– Priority Management of Reception of Hits on Several Message Objects at the
Same Time (Basic CAN Feature)
– Priority Management for Transmission
– Message Object Overrun Interrupt
– Time Triggered Communication
– Autobaud and Listening Mode
– Programmable Automatic Reply Mode
(1)
Crystal Frequency in X2 Mode
Enhanced 8-bit
MCU with CAN
Controller and
Flash Memory
AT89C51CC03
Rev. 4182K–CAN–05/06
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