AT89C51CC03CA-7CTUM ATMEL [ATMEL Corporation], AT89C51CC03CA-7CTUM Datasheet - Page 83

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AT89C51CC03CA-7CTUM

Manufacturer Part Number
AT89C51CC03CA-7CTUM
Description
Enhanced 8-bit MCU with CAN Controller and Flash Memory
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
Watchdog Programming
4182K–CAN–05/06
The three lower bits (S0, S1, S2) located into WDTPRG register permit to program the
WDT duration.
Table 42. Machine Cycle Count
To compute WD Time-Out, the following formula is applied:
Note:
The following table outlines the time-out value for Fosc
Table 43. Time-Out Computation
S2
0
0
0
0
1
1
1
1
S2
0
0
0
0
1
1
1
1
Svalue represents the decimal value of (S2 S1 S0)
F T i m e O u t
S1
0
0
1
1
0
0
1
1
S1
0
0
1
1
0
0
1
1
=
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
6
×
S0
0
1
0
1
0
1
0
1
2
W D X
S0
2
0
1
0
1
0
1
0
1
Fosc = 12 MHz
X
F o s c
2
131.07 ms
262.14 ms
524.29 ms
16.38 ms
32.77 ms
65.54 ms
(
1.05 s
2.10 s
2
14
×
2
S v a l u e
)
XTAL
Fosc = 16 MHz
Machine Cycle Count
196.56 ms
393.12 ms
786.24 ms
12.28 ms
24.57 ms
49.14 ms
98.28 ms
1.57 s
= 12 MHz in X1 mode
AT89C51CC03
2
2
2
2
2
2
2
2
14
15
16
17
18
19
20
21
Fosc = 20 MHz
157.28 ms
314.56 ms
629.12 ms
19.66 ms
39.32 ms
78.64 ms
9.82 ms
1.25 s
83

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