AT89C51ID2-SMSIM ATMEL [ATMEL Corporation], AT89C51ID2-SMSIM Datasheet
AT89C51ID2-SMSIM
Related parts for AT89C51ID2-SMSIM
AT89C51ID2-SMSIM Summary of contents
Page 1
... Temperature Ranges: Industrial (-40 to +85 C) • Packages: PLCC44, VQFP44, PLCC68 Note: 1. Contact Atmel Sales for availability. Description AT89C51ID2 is a high performance CMOS Flash version of the 80C51 CMOS single chip 8-bit microcontroller. It contains a 64 Kbytes Flash memory block for program and for data. Power Supply CC (1) ...
Page 2
... V pin. CC The AT89C51ID2 retains all features of the Atmel 80C52 with 256 bytes of internal RAM, a 10-source 4-level interrupt controller and three timer/counters. In addition, the AT89C51ID2 has a Programmable Counter Array, an XRAM of 1792 bytes, a Hardware Watchdog Timer, SPI and Keyboard, a more versatile serial channel that facilitates multiprocessor communication (EUART) and a speed improvement mechanism (X2 mode) ...
Page 3
... IB-bus CPU Parallel I/O Ports & Timer 0 INT External Bus Timer 1 Ctrl Port 0 Port 1 Port 2 (2) (2) (2) (2) (1): Alternate function of Port 1 (2): Alternate function of Port 3 (3): Alternate function of Port I2 AT89C51ID2 (1) (1) (1) (1) (1) Watch XRAM Dog PCA Keyboard Timer2 1792 x 8 POR PFD ...
Page 4
... SFR Mapping AT89C51ID2 4 The Special Function Registers (SFRs) of the AT89C51ID2 fall into the following categories: • C51 core registers: ACC, B, DPH, DPL, PSW, SP • I/O port registers: P0, P1, P2, P3, PI2 • Timer registers: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2, RCAP2L, RCAP2H • ...
Page 5
... M0 XRS2 ENBOO - - - ET2 PPCH PT2H PSH - PPCL PT2L PSL - - - - - - - - AT89C51ID2 RS0 GF1 GF0 PD IDL EXTRA XRS1 XRS0 AO M GF3 0 - DPS - - - - - - - CKS - SCLKT0 OscBEn OscAEn ET1 EX1 ET0 EX0 - ESPI EI2C ...
Page 6
... WatchDog Timer Program T2CON C8h Timer/Counter 2 control T2MOD C9h Timer/Counter 2 Mode Timer/Counter 2 Reload/Capture RCAP2H CBh High byte Timer/Counter 2 Reload/Capture RCAP2L CAh Low byte TH2 CDh Timer/Counter 2 High Byte TL2 CCh Timer/Counter 2 Low Byte AT89C51ID2 FPL3 FPL2 FPL1 FPL0 ...
Page 7
... CCAP3L5 CCAP3L4 CCAP4L7 CCAP4L6 CCAP4L5 CCAP4L4 FE/SM0 SM1 SM2 SPR2 SPEN SSDIS SPIF WCOL SSERR SPD7 SPD6 SPD5 AT89C51ID2 CCF3 CCF2 CCF1 - CPS1 CPS0 MAT0 TOG0 PWM0 MAT1 TOG1 PWM1 MAT2 TOG2 PWM2 MAT3 TOG3 PWM3 MAT4 TOG4 ...
Page 8
... SSADR 96h Synchronous Serial Address Table 12. Keyboard Interface SFRs Mnemonic Add Name KBLS 9Ch Keyboard Level Selector KBE 9Dh Keyboard Input Enable KBF 9Eh Keyboard Flag Register AT89C51ID2 SSCR2 SSPE SSSTA SSSTO SSC4 SSC3 SSC2 SSC1 SSD7 SSD6 SSD5 ...
Page 9
... SSCS 0000 0000 1111 1000 TL0 TL1 TH0 0000 0000 0000 0000 0000 0000 DPL DPH 0000 0000 0000 0000 2/A 3/B 4/C Reserved AT89C51ID2 5/D 6/E 7/F CCAP3H CCAP4H XXXX XXXX XXXX XXXX CCAP3L CCAP4L XXXX XXXX XXXX XXXX CCAPM3 CCAPM4 X000 0000 X000 0000 TH2 ...
Page 10
... P0.6/AD6 36 P0.7/AD7 PI2.0/SCL 33 ALE/PROG 32 PSEN 31 P2.7/A15 30 P2.6/A14 29 P2.5/A13 AT89C51ID2 28 6 VQFP44 1 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA PI2.0/SCL ALE/PROG PSEN P2 ...
Page 11
... P4.0 20 P1.1/T2EX/SS# 21 P1.2/ECI 22 P1.3/CEX0 23 P4.1 24 P1.4/CEX1 25 P4 P2.4/A12 47 P2.3/A11 46 P4.7 45 P2.2/A10 44 P2.1/A9 43 P2.0/A8 42 P4.6 41 NIC VQFP64 40 VSS 39 P4.5 38 XTAL1 37 XTAL2 36 P3.7/RD# 35 P4.4 34 P3.6/WR# 33 P4.3 AT89C51ID2 60 P5.0 59 P2.4/A12 58 P2.3/A11 57 P4.7 56 P2.2/A10 55 P2.1/A9 54 P2.0/A8 AT89C51ID2 53 P4.6 PLCC68 52 NIC 51 VSS 50 P4.5 49 XTAL1 48 XTAL2 47 P3.7/RD# 46 P4.4 45 P3.6/WR# 44 P4.3 NIC: Not Internaly Connected 11 ...
Page 12
... As inputs, Port 1 pins that are externally pulled 19, 20 low will source current because of the internal pull-ups. Port 1 also receives the low-order address byte during memory programming and verification. Alternate functions for AT89C51ID2 Port 1 include I/O P1.0: Input/Output I/O T2 (P1 ...
Page 13
... Port 5: Port 8-bit bidirectional I/O port with internal pull-ups. Port 3 52, 62, pins that have 1s written to them are pulled high by the internal pull-ups I/O 10, 13, 63 and can be used as inputs. As inputs, Port 5 pins that are externally pulled 16 7 low will source current because of the internal pull-ups. AT89C51ID2 13 ...
Page 14
... RST 10 4 ALE/PROG 33 27 PSEN AT89C51ID2 14 Type VQFP64 Name and Function Port I2: Port open drain. It can be used as inputs (must be polar 57, 26 ized to Vcc with external resistor to prevent any parasitic current consump- tion I/O SCL (PI2.0): 2-wire Serial Clock ...
Page 15
... Cleared, CPU and peripherals connected to OSCB 0 CKS Set, CPU and peripherals connected to OSCA Programmed by hardware after a Power-up regarding Hardware Security Byte (HSB).HSB.OSC (Default setting, OSCA selected) Reset Value = 0000 000’HSB.OSC’b (see Hardware Security Byte (HSB)) Not bit addressable AT89C51ID2 ...
Page 16
... AT89C51ID2 16 Table 16. OSCCON Register OSCCON- Oscillator Control Register (86h Bit Bit Number Mnemonic Description 7 - Reserved 6 - Reserved 5 - Reserved 4 - Reserved 3 - Reserved Sub Clock Timer0 Cleared by software to select T0 pin 2 SCLKT0 Set by software to select T0 Sub Clock Cleared by hardware after a Power Up OscB enable bit Set by software to run OscB ...
Page 17
... Power-Down mode bit 1 PD Cleared by hardware when reset occurs. Set to enter power-down mode. Idle mode bit 0 IDL Cleared by hardware when interrupt or reset occurs. Set to enter idle mode. Reset Value = 00X1 0000b Not bit addressable AT89C51ID2 POF GF1 GF0 IDL 17 ...
Page 18
... OscA XtalA2 OscAEn OSCCON PwdOscB XtalB1 OscB XtalB2 OscBEn OSCCON Operating Modes Reset Functional Modes Normal Modes AT89C51ID2 18 Reload Reset CKRL 1 8-bit :2 0 Prescaler-Divider X2 CKCON0 CKRL=0xFF? A hardware RESET puts the Clock generator in the following state: The selected oscillator depends on OSC bit in Hardware Security Byte (HSB). ...
Page 19
... AT89C51ID2 CKS Selected Mode Comment NORMAL MODE Default mode after power- OscB stopped Warm Reset NORMAL MODE Default mode after power- OscB running Warm Reset + OscB running NORMAL MODE 0 OscB running and selected ...
Page 20
... Design Considerations Oscillators Control Prescaler Divider AT89C51ID2 20 Table 19. Overview (Continued) PCON.1 PCON.0 OscBEn OscAEn • PwdOscA and PwdOscB signals are generated in the Clock generator and used to control the hard blocks of oscillators A and B. • PwdOscA =’1’ stops OscA • ...
Page 21
... The SCLKT0 bit in OSCCON register allows to select Timer 0 Subsidiary clock. SCLKT0 = 0: Timer 0 uses the standard T0 pin as clock input (Standard mode) SCLKT0 = 1: Timer 0 uses the special Sub Clock as clock input, this feature can be use as periodic interrupt for time clock. AT89C51ID2 F OSCA ---------------------------------------------- - ...
Page 22
... ALE disabling • Enhanced features on the UART and the timer 2 The AT89C51ID2 core needs only 6 clock periods per machine cycle. This feature called ‘X2’ provides the following advantages: • Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power. ...
Page 23
... Table 20.) and SPIX2 bit in the CKCON1 register (see Table 21) allows a switch from standard peripheral speed (12 clock periods per peripheral clock cycle) to fast periph- eral speed (6 clock periods per peripheral clock cycle). These bits are active only in X2 mode. AT89C51ID2 STD Mode 23 ...
Page 24
... AT89C51ID2 24 Table 20. CKCON0 Register CKCON0 - Clock Control Register (8Fh TWIX2 WDX2 PCAX2 Bit Bit Number Mnemonic Description 2-wire clock (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect) 7 TWIX2 Cleared to select 6 clock periods per peripheral clock cycle. ...
Page 25
... SPI (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect). 0 SPIX2 Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. Reset Value = XXXX XXX0b Not bit addressable AT89C51ID2 ...
Page 26
... Dual Data Pointer Register DPTR Figure 6. Use of Dual Pointer 7 AUXR1(A2H) AT89C51ID2 26 The additional data pointer can be used to speed up code execution and reduce code size. The dual DPTR structure is a way by which the chip will specify the address of an exter- nal data memory location. There are two 16-bit DPTR registers that address the external memory, and a single bit called DPS = AUXR1 ...
Page 27
... A3 INC DPTR ; increment SOURCE address 000C 05A2 INC AUXR1 ; switch data pointers 000E F0 MOVX @DPTR,A ; write the byte to DEST 000F A3 INC DPTR ; increment DEST address 0010 70F6JNZ LOOP ; check for 0 terminator 0012 05A2 INC AUXR1 ; (optional) restore DPS AT89C51ID2 ...
Page 28
... AT89C51ID2 28 INC is a short (2 bytes) and fast (12 clocks) way to manipulate the DPS bit in the AUXR1 SFR. However, note that the INC instruction does not directly force the DPS bit to a par- ticular state, but simply toggles it. In simple routines, such as the block move example, only the fact that DPS is toggled in the proper sequence matters, not its actual value. In other words, the block move routine works the same whether DPS is ’ ...
Page 29
... AT89C51ID2 devices have expanded RAM in external data space configurable up to 1792bytes (see Table 23.). The AT89C51ID2 has internal data memory that is mapped into four separate segments. The four segments are: 1. The Lower 128 bytes of RAM (addresses 00h to 7Fh) are directly and indirectly addressable ...
Page 30
... AT89C51ID2 30 useful if external peripherals are mapped at addresses already used by the internal XRAM. • With EXTRAM = 0, the XRAM is indirectly addressed, using the MOVX instruction in combination with any of the registers R0 the selected bank or DPTR. An access to XRAM will not affect ports P0, P2, P3.6 (WR) and P3.7 (RD). For example, with EXTRAM = 0, MOVX @R0, # data where R0 contains 0A0H, accesses the XRAM at address 0A0H rather than external memory ...
Page 31
... ALE Output bit Cleared, ALE is emitted at a constant rate of 1/6 the oscillator frequency (or 1 mode is used). (default) Set, ALE is active only during a MOVX or MOVC instruction is used. Reset Value = XX00 10’HSB. XRAM’0b Not bit addressable AT89C51ID2 XRS2 XRS1 XRS0 0 256 bytes ...
Page 32
... The Reset input can be used to force a reset pulse longer than the internal reset con- trolled by the Power Monitor. RST input has a pull-down resistor allowing power-on reset by simply connecting an external capacitor to V value and input characteristics are discussed in the Section “DC Characteristics” of the AT89C51ID2 datasheet. Figure 9. Reset Circuitry and Power-On Reset RST VSS a ...
Page 33
... RST pin. In order to properly propagate this pulse to the rest of the application in case of external capacitor or power-supply supervisor circuit resistor must be added as shown Figure 10. Figure 10. Recommended Reset Output Schematic VDD + RST VDD 1K RST VSS AT89C51ID2 AT89C51ID2 To other on-board circuitry 33 ...
Page 34
... This is achieved by applying an internal reset to them. By generating the Reset the Power Monitor insures a correct start up when AT89C51ID2 is powered up. In order to startup and maintain the microcontroller in correct operating mode stabilized in the V ...
Page 35
... XTAL clock input. The internal reset will remain asserted until the Xtal1 lev- els are above and below VIH and VIL. Further more. An internal counter will count 1024 clock periods before the reset is de-asserted. If the internal power supply falls below a safety level, a reset is immediately asserted. AT89C51ID2 t 35 ...
Page 36
... Auto-Reload Mode AT89C51ID2 36 The Timer 2 in the AT89C51ID2 is the standard C52 Timer 16-bit timer/counter: the count is maintained by two eight-bit timer registers, TH2 and TL2 are cascaded controlled by T2CON (Table 24) and T2MOD (Table 25) registers. Timer 2 operation is similar to Timer 0 and Timer 1.C/T2 selects F (timer operation) or external pin T2 (counter operation) as the timer clock input ...
Page 37
... To start the timer, set TR2 run control bit in T2CON register possible to use Timer baud rate generator and a clock generator simulta- neously. For this configuration, the baud rates and clock frequencies are not independent since both functions use the values in the RCAP2H and RCAP2L registers. AT89C51ID2 ...
Page 38
... AT89C51ID2 38 Figure 14. Clock-Out Mode C/ FCLK PERIPH T2 T2EX TR2 T2CON TL2 2 TH (8-bit) (8-bit) RCAP2H RCAP2L (8-bit) (8-bit) Toggle Q D T2OE T2MOD EXF2 T2CON EXEN2 T2CON OVER- FLOW TIMER 2 INTERRUPT 4289A–8051–09/03 ...
Page 39
... Timer 2 Capture/Reload bit If RCLK=1 or TCLK=1, CP/RL2# is ignored and timer is forced to auto-reload on Timer 2 overflow. 0 CP/RL2# Cleared to auto-reload on Timer 2 overflows or negative transitions on T2EX pin if EXEN2=1. Set to capture on negative transitions on T2EX pin if EXEN2=1. Reset Value = 0000 0000b Bit addressable AT89C51ID2 TCLK EXEN2 TR2 C/T2 CP/RL2# ) ...
Page 40
... AT89C51ID2 40 Table 25. T2MOD Register T2MOD - Timer 2 Mode Control Register (C9h Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. Reserved 6 - The value read from this bit is indeterminate. Do not set this bit. Reserved ...
Page 41
... CPS1 and CPS0 bits in the CMOD register (Table 26) and can be programmed to run at: peripheral clock frequency (F • 1/6 the peripheral clock frequency (F • 1/2 the • The Timer 0 overflow • The input on the ECI pin (P1.2) AT89C51ID2 ) 6 CLK PERIPH ) 2 CLK PERIPH External I/O Pin P1.2 / ECI P1.3 / CEX0 P1.4 / CEX1 P1.5 / CEX2 P1 ...
Page 42
... Figure 15. PCA Timer/Counter Fclk periph /6 Fclk periph / 2 T0 OVF P1.2 Idle AT89C51ID2 bit up/down counter CIDL WDTE CPS1 CPS0 CF CR CCF4 CCF3 CCF2 CCF1 CCF0 To PCA modules overflow It CL CMOD ECF 0xD9 CCON 0xD8 4289A–8051–09/03 ...
Page 43
... Bit CR (CCON.6) must be set by software to run the PCA. The PCA is shut off by clearing this bit. • Bit CF: The CF bit (CCON.7) is set when the PCA counter overflows and an interrupt will be generated if the ECF bit in the CMOD register is set. The CF bit can only be cleared by software. AT89C51ID2 ...
Page 44
... AT89C51ID2 44 • Bits 0 through 4 are the flags for the modules (bit 0 for module 0, bit 1 for module 1, etc.) and are set by hardware when either a match or a capture occurs. These flags also can only be cleared by software. Table 27. CCON Register CCON - PCA Counter Control Register (D8h) ...
Page 45
... CAPP bit enables the positive edge. If both bits are set both edges will be enabled and a capture will occur for either transition. • The last bit in the register ECOM (CCAPMn.6) when set enables the comparator function. AT89C51ID2 CCON 0xD8 To Interrupt priority decoder IE ...
Page 46
... AT89C51ID2 46 Table 28 shows the CCAPMn settings for the various PCA functions. Table 28. CCAPMn Registers (n = 0-4) CCAPM0 - PCA Module 0 Compare/Capture Control Register (0DAh) CCAPM1 - PCA Module 1 Compare/Capture Control Register (0DBh) CCAPM2 - PCA Module 2 Compare/Capture Control Register (0DCh) CCAPM3 - PCA Module 3 Compare/Capture Control Register (0DDh) ...
Page 47
... Bit Bit Number Mnemonic Description PCA Module n Compare/Capture Control 7-0 - CCAPnH Value Reset Value = 0000 0000b Not bit addressable AT89C51ID2 TOGn PWMm ECCFn Module Function Operation 16-bit capture by a positive-edge trigger on CEXn 16-bit capture by a negative trigger ...
Page 48
... AT89C51ID2 48 Table 31. CCAPnL Registers (n = 0-4) CCAP0L - PCA Module 0 Compare/Capture Control Register Low (0EAh) CCAP1L - PCA Module 1 Compare/Capture Control Register Low (0EBh) CCAP2L - PCA Module 2 Compare/Capture Control Register Low (0ECh) CCAP3L - PCA Module 3 Compare/Capture Control Register Low (0EDh) CCAP4L - PCA Module 4 Compare/Capture Control Register Low (0EEh) ...
Page 49
... CCAPMn register. The PCA timer will be compared to the module’s capture registers and when a match occurs an interrupt will occur if the CCFn (CCON SFR) and the ECCFn (CCAPMn SFR) bits for the module are both set (See Figure 18). AT89C51ID2 CCON 0xD8 ...
Page 50
... Figure 18. PCA Compare Mode and PCA Watchdog Timer Write to CCAPnL Reset Write to CCAPnH Enable 1 0 High Speed Output Mode AT89C51ID2 50 CF CCF4 CR CCAPnH CCAPnL Match 16 bit comparator CH CL PCA counter/timer ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn CIDL WDTE Before enabling ECOM bit, CCAPnL and CCAPnH should be set with a non zero value, otherwise an unwanted match could happen. Writing to CCAPnH will set the ECOM bit. Once ECOM set, writing CCAPnL will clear ECOM so that an unwanted match doesn’ ...
Page 51
... CCAPLn SFR the output will be low, when it is equal to or greater than the output will be high. When CL overflows from FF to 00, CCAPLn is reloaded with the value in CCAPHn. This allows updating the PWM without glitches. The PWM and ECOM bits in the module's CCAPMn register must be set to enable the PWM mode. AT89C51ID2 CCON 0xD8 PCA IT ...
Page 52
... PCA Watchdog Timer AT89C51ID2 52 Figure 20. PCA PWM Mode Overflow Enable ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn An on-board watchdog timer is available with the PCA to improve the reliability of the system without increasing chip count. Watchdog timers are useful for systems that are susceptible to noise, power glitches, or electrostatic discharge ...
Page 53
... Serial I/O Port Framing Error Detection 4289A–8051–09/03 The serial I/O port in the AT89C51ID2 is compatible with the serial I/O port in the 80C52. It provides both synchronous and asynchronous communication modes. It operates as a Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes (Modes 1, 2 and 3). Asynchronous transmission and reception can occur simultaneously ...
Page 54
... Automatic Address Recognition Given Address AT89C51ID2 54 Figure 23. UART Timings in Modes 2 and 3 RXD Start bit RI SMOD0=0 RI SMOD0=1 FE SMOD0=1 The automatic address recognition feature is enabled when the multiprocessor commu- nication feature is enabled (SM2 bit in SCON register is set). Implemented in hardware, automatic address recognition enhances the multiprocessor communication feature by allowing the serial port to examine the address of each incoming command frame ...
Page 55
... On reset, the SADDR and SADEN registers are initialized to 00h the given and broadcast addresses are XXXX XXXXb (all don’t-care bits). This ensures that the serial port will reply to any address, and so, that it is backwards compatible with the 80C51 microcontrollers that do not support automatic address recognition. AT89C51ID2 55 ...
Page 56
... Registers Baud Rate Selection for UART for Mode 1 and 3 AT89C51ID2 56 Table 34. SADEN Register SADEN - Slave Address Mask Register (B9h Reset Value = 0000 0000b Not bit addressable Table 35. SADDR Register SADDR - Slave Address Register (A9h Reset Value = 0000 0000b Not bit addressable The Baud Rate Generator for transmit and receive clocks can be selected separately via the T2CON and BDRCON registers ...
Page 57
... SPD • The baud rate for UART is token by formula: SMOD1 2 F PER Baud_Rate = (1-SPD (256 -BRL) SMOD1 2 F PER BRL = 256 - (1-SPD Baud_Rate AT89C51ID2 TBCK RBCK Clock Source (BDRCON) UART Timer Timer Timer Timer ...
Page 58
... AT89C51ID2 58 Table 37. SCON Register SCON - Serial Control Register (98h FE/SM0 SM1 SM2 Bit Bit Number Mnemonic Description Framing Error bit (SMOD0=1) Clear to reset the error state, not cleared by a valid stop bit Set by hardware when an invalid stop bit is detected. ...
Page 59
... UART, thanks to the bit SRC located in BDRCON register (Table 46.) Table 40. SADEN Register SADEN - Slave Address Mask Register for UART (B9h Reset Value = 0000 0000b Table 41. SADDR Register SADDR - Slave Address Register for UART (A9h Reset Value = 0000 0000b AT89C51ID2 F = 24MHz OSC Error (%) BRL 1.23 243 1.23 230 1.23 217 1.23 204 0 ...
Page 60
... AT89C51ID2 60 Table 42. SBUF Register SBUF - Serial Buffer Register for UART (99h Reset Value = XXXX XXXXb Table 43. BRL Register BRL - Baud Rate Reload Register for the internal baud rate generator, UART (9Ah Reset Value = 0000 0000b 4289A– ...
Page 61
... Timer 2 Capture/Reload bit If RCLK=1 or TCLK=1, CP/RL2# is ignored and timer is forced to auto-reload on timer 2 overflow. 0 CP/RL2# Cleared to auto-reload on timer 2 overflows or negative transitions on T2EX pin if EXEN2=1. Set to capture on negative transitions on T2EX pin if EXEN2=1. Reset Value = 0000 0000b Bit addressable AT89C51ID2 TCLK EXEN2 TR2 C/T2# Description 1 ...
Page 62
... AT89C51ID2 62 Table 45. PCON Register PCON - Power Control Register (87h SMOD1 SMOD0 - Bit Bit Number Mnemonic Serial port Mode bit 1 for UART 7 SMOD1 Set to select double baud rate in mode Serial port Mode bit 0 for UART 6 SMOD0 Cleared to select SM0 bit in SCON register. ...
Page 63
... Baud Rate Source select bit in Mode 0 for UART Cleared to select F 0 SRC mode). Set to select the internal Baud Rate Generator for UARTs in mode 0. Reset Value = XXX0 0000b Not bit addressablef AT89C51ID2 BRR TBCK RBCK SPD /12 as the Baud Rate Generator (F ...
Page 64
... Individual Enable AT89C51ID2 64 The AT89C51ID2 has a total of 10 interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (timers 0, 1 and 2), the serial port interrupt, SPI interrupt, Keyboard interrupt and the PCA global interrupt. These interrupts are shown in Figure 26. ...
Page 65
... If interrupt requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced. Thus within each priority level there is a second priority structure determined by the polling sequence. AT89C51ID2 IPL. x Interrupt Level Priority 0 0 (Lowest) ...
Page 66
... AT89C51ID2 66 Table 48. IENO Register IEN0 - Interrupt Enable Register (A8h ET2 Bit Bit Number Mnemonic Description Enable All interrupt bit 7 EA Cleared to disable all interrupts. Set to enable all interrupts. PCA interrupt enable bit 6 EC Cleared to disable. Set to enable. Timer 2 overflow interrupt Enable bit ...
Page 67
... PX1L Refer to PX1H for priority level. Timer 0 overflow interrupt Priority bit 1 PT0L Refer to PT0H for priority level. External interrupt 0 Priority bit 0 PX0L Refer to PX0H for priority level. Reset Value = X000 0000b Bit addressable AT89C51ID2 PSL PT1L PX1L PT0L 1 0 PX0L 67 ...
Page 68
... AT89C51ID2 68 Table 50. IPH0 Register IPH0 - Interrupt Priority High Register (B7h PPCH PT2H Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. PCA interrupt Priority high bit. PPCHPPCLPriority Level 0 0Lowest 6 PPCH ...
Page 69
... Set to enable SPI interrupt. TWI interrupt Enable bit 1 ETWI Cleared to disable TWI interrupt. Set to enable TWI interrupt. Keyboard interrupt Enable bit 0 EKBD Cleared to disable keyboard interrupt. Set to enable keyboard interrupt. Reset Value = XXXX X000b Bit addressable AT89C51ID2 ESPI ETWI 0 EKBD 69 ...
Page 70
... AT89C51ID2 70 Table 52. IPL1 Register IPL1 - Interrupt Priority Register (B2h) Table 53 Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. Reserved 6 - The value read from this bit is indeterminate. Do not set this bit. ...
Page 71
... TWI interrupt Priority High bit TWIH TWILPriority Level 0 1 TWIH Keyboard interrupt Priority High bit KB DH KBDLPriority Level 0 0 KBDH Reset Value = XXXX X000b Not bit addressable AT89C51ID2 SPIH 0 Lowest Highest 0 Lowest Highest 0 Lowest Highest 1 ...
Page 72
... Interrupt Sources and Vector Addresses AT89C51ID2 72 Table 55. Interrupt Sources and Vector Addresses Number Polling Priority Interrupt Source Keyboard Interrupt Request Reset INT0 IE0 Timer 0 TF0 INT1 IE1 Timer 1 IF1 UART ...
Page 73
... Idle mode. The contents of the status of the Port pins during Idle mode is detailed in Table 56. To enter Idle mode, set the IDL bit in PCON register (see Table 57). The AT89C51ID2 enters Idle mode upon execution of the instruction that sets IDL bit. The instruction that sets IDL bit is the last instruction executed ...
Page 74
... Take care, however, that VDD is not reduced until Power-Down mode is invoked. To enter Power-Down mode, set PD bit in PCON register. The AT89C51ID2 enters the Power-Down mode upon execution of the instruction that sets PD bit. The instruction that sets PD bit is the last instruction executed. ...
Page 75
... Idle (external Floating Data code) Power- Down(inter Data Data nal code) Power- Down Floating Data (external code) AT89C51ID2 , but does not affect the internal SFRs Port 2 Port 3 Port 4 High High High Data Data Data Data Data Data Data Data Data ...
Page 76
... Registers AT89C51ID2 76 Table 57. PCON Register PCON (S87:h) Power configuration Register Bit Bit Number Mnemonic Description Reserved 7-5 - The value read from these bits is indeterminate. Do not set these bits. Power-Off Flag Cleared to recognize next reset type. 4 POF Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set by software ...
Page 77
... Interrupt Power Reduction Mode 4289A–8051–09/03 The AT89C51ID2 implements a keyboard interface allowing the connection matrix keyboard based on 8 inputs with programmable interrupt capability on both high or low level. These inputs are available as alternate function of P1 and allow to exit from idle and power down modes. ...
Page 78
... Registers AT89C51ID2 78 Table 58. KBF Register KBF-Keyboard Flag Register (9Eh KBF7 KBF6 KBF5 Bit Bit Number Mnemonic Description Keyboard line 7 flag Set by hardware when the Port line 7 detects a programmed level. It generates a 7 KBF7 Keyboard interrupt request if the KBKBIE. 7 bit in KBIE register is set. ...
Page 79
... Cleared to enable standard I/O pin. Set to enable KBF. 1 bit in KBF register to generate an interrupt request. Keyboard line 0 Enable bit 0 KBE0 Cleared to enable standard I/O pin. Set to enable KBF. 0 bit in KBF register to generate an interrupt request. Reset Value= 0000 0000b AT89C51ID2 KBE4 KBE3 KBE2 KBE1 ...
Page 80
... AT89C51ID2 80 Table 60. KBLS Register KBLS-Keyboard Level Selector Register (9Ch KBLS7 KBLS6 KBLS5 Bit Bit Number Mnemonic Description Keyboard line 7 Level Selection bit 7 KBLS7 Cleared to enable a low level detection on Port line 7. Set to enable a high level detection on Port line 7. Keyboard line 6 Level Selection bit ...
Page 81
... Kbit/s in standard mode. Various communication configuration can be designed using this bus. Figure 30 shows a typical 2-wire bus configuration. All the devices connected to the bus can be master and slave. Figure 30. 2-wire Bus Configuration device1 device2 device3 SCL SDA AT89C51ID2 ... deviceN 81 ...
Page 82
... Figure 31. Block Diagram Input Filter SDA PI2.1 Output Stage Input Filter SCL PI2.0 Output Stage AT89C51ID2 82 SSADR Address Register Comparator SSDAT Shift Register Arbitration & Sink Logic Timing & Control logic Serial clock generator Timer 1 overflow Control Register SSCON Status Status ...
Page 83
... Slave transmitter • Slave receiver Data transfer in each mode of operation is shown in Table to Table 69 and Figure 33. to Figure 36.. These figures contain the following abbreviations START condition R : Read bit (high level at SDA) AT89C51ID2 acknowledgement acknowledgement signal from receiver signal from receiver 1 2 3-8 9 ...
Page 84
... Master Transmitter Mode Master Receiver Mode AT89C51ID2 84 W: Write bit (low level at SDA) A: Acknowledge bit (low level at SDA) A: Not acknowledge bit (high level at SDA) Data: 8-bit data byte P : STOP condition In Figure 33 to Figure 36, circles are used to indicate when the serial interrupt flag is set. ...
Page 85
... In the slave transmitter mode, a number of data bytes are transmitted to a master receiver (Figure 36). Data transfer is initialized as in the slave receiver mode. When SSADR and SSCON have been initialized, the TWI module waits until it is addressed by AT89C51ID2 ...
Page 86
... Miscellaneous States Notes AT89C51ID2 86 its own slave address followed by the data direction bit which must be at logic 1 (R) for TWI to operate in the slave transmitter mode. After its own slave address and the R bit have been received, the serial interrupt flag is set and a valid status code can be read from SSCS ...
Page 87
... A P 20h Other master continues 38h Other master A continues 68h 78h B0h Data A n AT89C51ID2 A P 28h S SLA 10h A P 30h Other master continues 38h To corresponding states in slave mode Any number of data bytes and their associated acknowledge bits ...
Page 88
... Write data byte No SSDAT action Data byte has been 30h transmitted; NOT ACK No SSDAT action has been received No SSDAT action No SSDAT action Arbitration lost in 38h SLA+W or data bytes No SSDAT action AT89C51ID2 88 Application software response To SSCON SSSTA SSSTO SSI SSAA ...
Page 89
... Other master A continues 68h 78h B0h Any number of data bytes and their associated Data A acknowledge bits This number (contained in SSCS) corresponds defined state of the 2-wire bus AT89C51ID2 A P Data 58h S SLA R 10h W MT Other master A continues 38h To corresponding ...
Page 90
... Data byte has been 50h received; ACK has been returned Read data byte Read data byte Data byte has been Read data byte 58h received; NOT ACK has been returned Read data byte AT89C51ID2 90 Application software response To SSCON SSSTA SSSTO SSI SSAA ...
Page 91
... A 60h A 68h General Call A 70h A 78h Any number of data bytes and their associated Data A acknowledge bits This number (contained in SSCS) corresponds defined state of the 2-wire bus AT89C51ID2 Data A Data A 80h 80h 88h Data Data A A 90h ...
Page 92
... Previously addressed with own SLA+W; data has been 88h received; NOT ACK has been returned Previously addressed with general call; data has been 90h received; ACK has been returned AT89C51ID2 92 Application Software Response To/from SSDAT To SSCON STA STO SI No SSDAT action or X ...
Page 93
... No SSDAT action SSDAT action AT89C51ID2 AA Next Action Taken By 2-wire Software Switched to the not addressed slave mode; no recognition of own SLA or GCA 0 Switched to the not addressed slave mode; own SLA will be recognised; GCA will be recognised if 1 GC=logic 1 Switched to the not addressed slave mode; no recognition of own SLA or GCA ...
Page 94
... Arbitration lost in SLA+R/W as master; own SLA+R has been B0h received; ACK has been returned Data byte in SSDAT has been B8h transmitted; NOT ACK has been received AT89C51ID2 94 A Data SLA R A8h A B0h Any number of data bytes and their associated Data ...
Page 95
... SI= 0 Bus error due SSDAT 00h illegal START or action STOP condition AT89C51ID2 SI AA Next Action Taken By 2-wire Software Switched to the not addressed slave mode; no recognition of own SLA or GCA 0 0 Switched to the not addressed slave mode; own SLA will be recognised; GCA will be recognised if ...
Page 96
... Registers AT89C51ID2 96 Table 70. SSCON Register SSCON - Synchronous Serial Control register (93h CR2 SSIE STA Bit Bit Number Mnemonic Description Control Rate bit 2 7 CR2 See Table 64. Synchronous Serial Interface Enable bit 6 SSIE Clear to disable the TWI module. Set to enable the TWI module. ...
Page 97
... Mnemonic Description 7 A7 Slave Address bit Slave Address bit Slave Address bit Slave Address bit Slave Address bit Slave Address bit Slave Address bit 1 AT89C51ID2 SC1 SC0 ...
Page 98
... AT89C51ID2 98 Bit Bit Number Mnemonic Description General Call bit 0 GC Clear to disable the general call address recognition. Set to enable the general call address recognition. 4289A–8051–09/03 ...
Page 99
... MOSI and MISO lines driven by the Master for eight clock cycles which allows to exchange one byte on the serial lines. Each Slave peripheral is selected by one Slave Select pin (SS). This signal must stay low for any message for a Slave obvious that only one Master (SS high level) can AT89C51ID2 Slave 1 Slave 3 Slave 2 ...
Page 100
... Baud rate AT89C51ID2 100 drive the network. The Master may select each Slave device by software through port pins (Figure 37). To prevent bus conflicts on the MISO line, only one slave should be selected at a time by the Master for a transmission Master configuration, the SS line can be used in conjunction with the MODF flag in the SPI Status register (SPSTA) to prevent multiple masters from driving MOSI and SCK (See Error conditions) ...
Page 101
... When the Master device transmits data to the Slave device via the MOSI line, the Slave device responds by sending data to the Master device via the MISO line. This implies full-duplex transmission with both data out and data in synchronized with the same clock (Figure 39). AT89C51ID2 Internal Bus SPDAT Shift Register ...
Page 102
... Master mode Slave mode Transmission Formats AT89C51ID2 102 Figure 39. Full-Duplex Master-Slave Interconnection MISO 8-bit Shift register MOSI SPI SCK Clock Generator SS VDD Master MCU The SPI operates in Master mode when the Master bit, MSTR is set. Only one Master SPI device can initiate transmissions. Software begins the trans- mission from a Master SPI module by writing to the Serial Peripheral Data Register (SPDAT) ...
Page 103
... MOSI pin on the first SCK edge. Therefore the Slave uses the first SCK edge as a start transmission signal. The SS pin can remain low between transmis- sions (Figure 42). This format may be preffered in systems having only one Master and only one Slave driving the MISO data line. AT89C51ID2 ...
Page 104
... Mode Fault (MODF) Write Collision (WCOL) Overrun Condition Interrupts AT89C51ID2 104 The following flags in the SPSTA signal SPI error conditions: Mode Fault error in Master mode SPI indicates that the level on the Slave Select (SS) pin is inconsistent with the actual mode of the device. MODF is set to warn that there may have a multi-master conflict for system control ...
Page 105
... Set to have the SCK set to’1’ in idle low. Clock Phase Cleared to have the data sampled when the SCK leaves the idle 3 CPHA state (see CPOL). Set to have the data sampled when the SCK returns to idle state (see CPOL). AT89C51ID2 SPI CPU Interrupt Request MSTR CPOL ...
Page 106
... Serial Peripheral Status Register (SPSTA) AT89C51ID2 106 Bit Number Bit Mnemonic Description SPR2 2 SPR1 SPR0 1 1 Reset Value= 0001 0100b Not bit addressable The Serial Peripheral Status Register contains flags to signal the following conditions: • Data transfer complete • ...
Page 107
... Do not change SPR2, SPR1 and SPR0 • Do not change CPHA and CPOL • Do not change MSTR • Clearing SPEN would immediately disable the peripheral • Writing to the SPDAT will cause an overflow AT89C51ID2 ...
Page 108
... Hardware Watchdog Timer Using the WDT AT89C51ID2 108 The WDT is intended as a recovery method in situations where the CPU may be sub- jected to software upset. The WDT consists of a 14-bit counter and the WatchDog Timer ReSeT (WDTRST) SFR. The WDT is by default disabled from exiting reset. To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR location 0A6H ...
Page 109
... WDT just before entering powerdown. In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting the AT89C51ID2 while in Idle mode, the user should always set up a timer that will periodi- cally exit Idle, service the WDT, and re-enter Idle mode. ...
Page 110
... Pull ALE low while the device is in reset (RST high) and PSEN is high. • Hold ALE low as RST is deactivated. While the AT89C51ID2 is in ONCE mode, an emulator or test CPU can be used to drive the circuit Table 83 shows the status of the port pins during ONCE mode. Normal operation is restored when normal reset is applied. ...
Page 111
... Cleared by hardware when reset occurs. Set to enter power-down mode. Idle mode bit 0 IDL Cleared by hardware when interrupt or reset occurs. Set to enter idle mode. Reset Value = 00X1 0000b Not bit addressable AT89C51ID2 switch-on. A warm start reset occurs while POF GF1 GF0 rises from 0 to its nominal voltage ...
Page 112
... EEPROM Data Memory Write Data AT89C51ID2 112 The 2K bytes on-chip EEPROM memory block is located at addresses 0000h to 07FFh of the XRAM/ERAM memory space and is selected by setting control bits in the EECON register. A read or write access to the EEPROM memory is done with a MOVX instruction. Data is written by byte to the EEPROM memory block as for an external RAM memory. ...
Page 113
... Figure 44. Recommended EEPROM Data Write Sequence EEPROM Data Write EEPROM Data Mapping EECON = 02h (EEE=1) Exec: MOVX @DPTR, A EECON = 00h (EEE=0) AT89C51ID2 Sequence EEBusy Cleared? Save & Disable IT EA= 0 Data Write DPTR= Address ACC= Data EEPROM Mapping Restore IT ...
Page 114
... Read Data AT89C51ID2 114 The following procedure is used to read the data stored in the EEPROM memory: • Check EEBUSY flag • If the user application interrupts routines use XRAM memory space: Save and disable interrupts. • Load DPTR with the address to read • ...
Page 115
... EEPROM . Clear to map the XRAM space during MOVX. Programming Busy flag Set by hardware when programming is in progress. 0 EEBUSY Cleared by hardware when programming is done. Can not be set or cleared by software. Reset Value = XXXX XX00b Not bit addressable AT89C51ID2 EEE 0 EEBUSY ...
Page 116
... Reduced EMI Mode AT89C51ID2 116 The ALE signal is used to demultiplex address and data buses on port 0 when used with external program or data memory. Nevertheless, during internal code execution, ALE signal is still generated. In order to reduce EMI, ALE signal can be disabled by setting AO bit. The AO bit is located in AUXR register at bit location 0. As soon set, ALE is no longer output but remains active during MOVX and MOVC instructions and external fetches ...
Page 117
... EPROM programmer. The parallel programming method used by these devices is similar to that used by EPROM 87C51 but it is not identical and the commercially available programmers need to have support for the AT89C51ID2. The bootloader and the Application Programming Interface (API) routines are located in the BOOT ROM. ...
Page 118
... Software registers are in a special page of the Flash memory which can be accessed through the API or with the parallel programming modes. This page, called "Extra Flash Memory", is not in the internal Flash program memory addressing space. The only hardware register of the AT89C51ID2 is called Hardware Security Byte (HSB). Table 87. Hardware Security Byte (HSB ...
Page 119
... These registers are in the "Extra Flash Memory" part of the Flash memory. This block is also called "XAF" or eXtra Array Flash. They are accessed in the following ways: • Commands issued by the parallel memory programmer. • Commands issued by the ISP software. • Calls of API issued by the application software. Several software registers described in Table 89. AT89C51ID2 119 ...
Page 120
... The two lock bits provide different levels of protection for the on-chip code and data, when programmed as shown to Table 92. Default value Description FCh 101x 1011b 0FFh FFh 58h ATMEL D7h C51 X2, Electrically Erasable ECh AT89C51ID2 64KB AT89C51ID2 64KB, Revision EFh LB1 0 LB0 4289A–8051–09/03 ...
Page 121
... X: do not care WARNING: Security level 2 and 3 should only be programmed after Flash and code verification. AT89C51ID2 parts are delivered in standard with the ISP rom bootloader. After ISP or parallel programming, the possible contents of the Flash memory are sum- marized on the figure below: ...
Page 122
... Acronyms AT89C51ID2 122 The bootloader manages a communication according to a specific defined protocol to provide the whole access and service on Flash memory. Furthermore, all accesses and routines can be called from the user application. Figure 47. Diagram Context Description ...
Page 123
... Results are returned in the registers. The pur- pose on this process is to translate the registers values into internal Flash Memory Management. • Flash Memory Management This process manages low level access to flash memory (performs read and write access). AT89C51ID2 User Application User Call Management (API ) 123 ...
Page 124
... Bootloader Functionality Introduction AT89C51ID2 124 The bootloader can be activated by two means: Hardware conditions or regular boot process. The Hardware conditions ( PSEN = 0) during the Reset# falling edge force the on-chip bootloader execution. This allows an application to be built that will normally execute the end user’s code but can be manually forced into default ISP operation. ...
Page 125
... ENBOOT bit (AUXR1) is cleared Yes (PSEN = and ALE =1 or not connected) FCON = 00h Hardware condition? FCON = F0h BLJB=1 BLJB!= 0 ENBOOT=0 ? BLJB=0 ENBOOT=1 F800h yes = hardware boot FCON = 00h ? BSB = 00h ? SBV = FCh ? USER BOOT LOADER PC= [SBV]00h AT89C51ID2 conditions Atmel BOOT LOADER 125 ...
Page 126
... ISP Protocol Description Physical Layer Frame Description AT89C51ID2 126 The UART used to transmit information has the following configuration: • Character: 8-bit data • Parity: none • Stop: 2 bits • Flow control: none • Baudrate: autobaud is performed by the bootloader to compute the baudrate choosen by the host ...
Page 127
... Read only access allowed Write level 2 allowed Read only access allowed Read only access allowed Allowed Allowed Allowed AT89C51ID2 Level 1 Any access not allowed Any access not allowed Any access not allowed Read only access allowed Read only access allowed Read only access allowed ...
Page 128
... Full Chip Erase Checksum Error AT89C51ID2 128 The ISP command "Full Chip Erase" erases all User Flash memory (fills with FFh) and sets some bytes used by the bootloader at their default values: • BSB = FFh • SBV = FCh • SSB = FFh and finally erase the Software Security Bits The Full Chip Erase does not affect the bootloader. When a checksum error is detected send ‘ ...
Page 129
... This information is then used to pro- gram the baud rate in terms of timer counts based on the oscillator frequency. The ISP feature requires that an initial character (an uppercase U) be sent to the AT89C51ID2 to establish the baud rate. Table show the autobaud capability. ...
Page 130
... OK 9600 OK 19200 OK 38400 - 57600 - 115200 - Command Data Stream Protocol Figure 52. Command Flow Host Sends first character of the Frame Sends frame (made of 2 ASCII characters per byte) Echo analysis AT89C51ID2 130 2.4576 3 3.6864 All commands are sent using the same flow. Each frame sent by the host is echoed by the bootloader. " ...
Page 131
... F5 BOOTLOADER : 02 0000 F5 Writing Frame (write BSB to 55h) HOST : 03 0000 BOOTLOADER : 03 0000 AT89C51ID2 Bootloader Wait Write Command Checksum error Send Checksum error NO_SECURITY Send Security error Wait Programming Send COMMAND_OK ...
Page 132
... OR Wait Checksum Error COMMAND ABORTED Wait COMMAND_OK OR COMMAND FINISHED Wait Address not erased COMMAND FINISHED Example AT89C51ID2 132 Blank Check Command ’X’ & CR & LF ’.’ & CR & LF address & CR & LF Blank Check ok HOST : 05 0000 04 0000 7FFF 01 78 BOOTLOADER : 05 0000 04 0000 7FFF ...
Page 133
... Display Command ’X’ & CR & LF Send Checksum Error ’L’ & CR & LF Send Security Error Complet Frame "Address = " "Reading value" CR & LF AT89C51ID2 Bootloader Wait Display Command Checksum error RD_WR_SECURITY Read Data All data read Send Display Data All data read ...
Page 134
... Send Read Command OR Wait Checksum Error COMMAND ABORTED OR Wait Security Error COMMAND ABORTED Wait Value of Data COMMAND FINISHED AT89C51ID2 134 Display data from address 0000h to 0020h HOST : 05 0000 04 0000 0020 00 D7 BOOTLOADER : 05 0000 04 0000 0020 00 D7 BOOTLOADER 0000=-----data------ CR LF BOOTLOADER ...
Page 135
... Example 4289A–8051–09/03 Read function (read SBV) HOST : 02 0000 BOOTLOADER : 02 0000 Value . CR LF Atmel Read function (read Bootloader version) HOST : 02 0000 BOOTLOADER : 02 0000 Value . CR LF AT89C51ID2 135 ...
Page 136
... ISP Commands Summary AT89C51ID2 136 Table 95. ISP Commands Summary Command Command Name 00h Program Data 03h Write Function 04h Display Function data[0] data[1] Command Effect Program Nb Data Byte. Bootloader will accept up to 128 (80h) data bytes. The data bytes should be 128 byte page flash boundary ...
Page 137
... Table 95. ISP Commands Summary (Continued) Command Command Name 05h Read Function AT89C51ID2 data[0] data[1] Command Effect 00h Manufacturer Id 01h Device Id #1 00h 02h Device Id #2 03h Device Id #3 00h Read SSB 01h Read BSB 07h 02h Read SBV ...
Page 138
... XXh READ SBV 07h XXh AT89C51ID2 138 Several Application Program Interface (API) calls are available for use by an application program to permit selective erasing and programming of Flash pages. All calls are made through a common interface, PGM_MTP. The programming functions are selected by setting up the microcontroller’ ...
Page 139
... XXh none DPL=00h XXh ACC=ID1 DPL=01h XXh ACC=ID2 XXXXh XXh ACC=Boot_Version AT89C51ID2 Command Effect Read Device identifier 1 Read Device identifier 2 Read Device identifier 3 Erase block 0 Erase block 1 Erase block 2 Erase block 3 Erase block 4 Program up to 128 bytes in user flash. Remark: number of bytes to program is limited such as the Flash write remains in a single 128bytes page ...
Page 140
... Input High Voltage RST, XTAL1 IH1 V Output Low Voltage, ports Output Low Voltage, port 0, ALE, PSEN OL1 V Output High Voltage, ports Output High Voltage, port 0, ALE, PSEN OH1 AT89C51ID2 140 Note: + 0.5V CC (2) =2.7V to 5.5V MHz Min Typ -0.5 0 0.9 CC 0.7 V ...
Page 141
... Pins are not guaranteed to sink current greater OL Figure 57. I Test Condition, Active Mode RST EA (NC) XTAL2 CLOCK XTAL1 SIGNAL V SS AT89C51ID2 Max Unit (5) 250 k -50 10 -650 150 0.4 x Frequency (MHz 0.3 x Frequency (MHz 0.8 x Frequency (MHz ...
Page 142
... AC Parameters Explanation of the AC Symbols AT89C51ID2 142 Figure 58. I Test Condition, Idle Mode RST EA (NC) XTAL2 CLOCK XTAL1 SIGNAL V SS Figure 59. I Test Condition, Power-down Mode RST EA (NC) XTAL2 XTAL1 V SS Figure 60. Clock Signal Waveform for ...
Page 143
... Table 98. AC Parameters for a Fix Clock Symbol -M Min LHLL T 5 AVLL T 5 LLAX T LLIV T 5 LLPL T 50 PLPH T PLIV T 0 PXIX T PXIZ T AVIV T PLAZ AT89C51ID2 -L Max Min Max Units ...
Page 144
... AT89C51ID2 144 Table 99. AC Parameters for a Variable Clock Standard Symbol Type Clock T Min LHLL T Min AVLL T Min LLAX T Max LLIV T Min LLPL T Min PLPH T Max PLIV T Min x PXIX T Max PXIZ T Max AVIV ...
Page 145
... ALE LLWL T Address AVWL T Data Valid to WR Transition QVWX T Data Set- High QVWH T Data Hold After WR WHQX T RD Low to Address Float RLAZ High to ALE high WHLH AT89C51ID2 CLCL T PXAV T PXIZ A0-A7 INSTR IN ADDRESS A8-A15 145 ...
Page 146
... AT89C51ID2 146 Table 101. AC Parameters for a Fix Clock -M Symbol Min T 125 RLRH T 125 WLWH T RLDV T 0 RHDX T RHDZ T LLDV T AVDV T 45 LLWL T 70 AVWL T 5 QVWX T 155 QVWH T 10 WHQX T 0 RLAZ T 5 WHLH Table 102. AC Parameters for a Variable Clock Standard ...
Page 147
... XLXL T Output data set-up to clock rising edge QVHX T Output data hold after clock rising edge XHQX T Input data hold after clock rising edge XHDX T Clock rising edge to input data valid XHDV AT89C51ID2 T WHLH T WLWH T T WHQX QVWH DATA OUT T WHLH T RLRH ...
Page 148
... Shift Register Timing Waveforms 0 INSTRUCTION ALE CLOCK T QVXH OUTPUT DATA WRITE to SBUF INPUT DATA CLEAR RI External Clock Drive Waveforms AT89C51ID2 148 Table 104. AC Parameters for a Fix Clock -M Symbol Min T 300 XLXL T 200 QVHX T 30 XHQX T 0 XHDX T XHDV Table 105. AC Parameters for a Variable Clock ...
Page 149
... For timing purposes as port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded V occurs mA Valid in normal clock mode mode XTAL2 must be changed to XTAL2/2. AT89C51ID2 0 0 0.5 for a logic “1” and 0.45V for a logic “0”. ...
Page 150
... This propagation delay is dependent on variables such as temperature and pin loading. Propaga- tion also varies from output to output and component. Typically though (T delays are approximately 50 ns. The other signals are typically 85 ns. Propagation delays are incorporated in the AC specifications. AT89C51ID2 150 STATE5 STATE6 ...
Page 151
... Ordering Information 4289A–8051–09/03 Table 106. Possible Order Entries Part Number Supply Voltage AT89C51ID2-SLSIM AT89C51ID2-RLTIM 2.7V-5.5V (1) AT89C51ID2-SMSIM (1) AT89C51ID2-RDTIM Note: 1. For PLCC68 and VQFP64 packages, please contact Atmel sales office for availability. AT89C51ID2 Temperature Range Package Packing PLCC44 Stick VQFP44 Industrial PLCC68 ...
Page 152
... Packaging Information PLCC44 AT89C51ID2 152 4289A–8051–09/03 ...
Page 153
... VQFP44 4289A–8051–09/03 AT89C51ID2 153 ...
Page 154
... VQFP64 AT89C51ID2 154 4289A–8051–09/03 ...
Page 155
... PLCC68 4289A–8051–09/03 AT89C51ID2 155 ...
Page 156
... Table of Contents AT89C51ID2 156 Features................................................................................................. 1 Description ............................................................................................ 1 Block Diagram....................................................................................... 3 SFR Mapping......................................................................................... 4 Pin Configurations.............................................................................. 10 Oscillators ........................................................................................... 15 Overview............................................................................................................. 15 Registers............................................................................................................. 15 Functional Block Diagram................................................................................... 18 ............................................................................................................................ 18 Operating Modes ................................................................................................ 18 Design Considerations........................................................................................ 20 Timer 0: Clock Inputs.......................................................................................... 21 Enhanced Features............................................................................. 22 X2 Feature .......................................................................................................... 22 Dual Data Pointer Register DPTR...................................................... 26 Expanded RAM (XRAM) ..................................................................... 29 Registers............................................................................................................. 31 Reset .................................................................................................... 32 Introduction ......................................................................................................... 32 Reset Input ...
Page 157
... Signal Description............................................................................................... 99 Functional Description ...................................................................................... 101 Hardware Watchdog Timer .............................................................. 108 Using the WDT ................................................................................................. 108 WDT During Power Down and Idle................................................................... 109 ONCE(TM) Mode (ON Chip Emulation) ........................................... 110 Power-off Flag................................................................................... 111 EEPROM Data Memory..................................................................... 112 Write Data......................................................................................................... 112 Read Data......................................................................................................... 114 Registers........................................................................................................... 115 AT89C51ID2 157 ...
Page 158
... AT89C51ID2 158 Reduced EMI Mode........................................................................... 116 Flash Memory.................................................................................... 117 Features............................................................................................................ 117 Flash Programming and Erasure...................................................................... 117 Flash Registers and Memory Map.................................................................... 118 Flash Memory Status........................................................................................ 121 Memory Organization ....................................................................................... 121 Bootloader Architecture .................................................................................... 122 ISP Protocol Description................................................................................... 126 Functional Description ...................................................................................... 127 Flow Description ............................................................................................... 129 API Call Description ...
Page 159
Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 ...