AT89C51ID2-SMSIM ATMEL [ATMEL Corporation], AT89C51ID2-SMSIM Datasheet - Page 112
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AT89C51ID2-SMSIM
Manufacturer Part Number
AT89C51ID2-SMSIM
Description
8-bit Flash Microcontroller
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
1.AT89C51ID2-SMSIM.pdf
(159 pages)
- Current page: 112 of 159
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EEPROM Data
Memory
Write Data
112
AT89C51ID2
The 2K bytes on-chip EEPROM memory block is located at addresses 0000h to 07FFh
of the XRAM/ERAM memory space and is selected by setting control bits in the EECON
register.
A read or write access to the EEPROM memory is done with a MOVX instruction.
Data is written by byte to the EEPROM memory block as for an external RAM memory.
The following procedure is used to write to the EEPROM memory:
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Figure 44 represents the optimal write sequence to the on-chip EEPROM data memory.
Check EEBUSY flag
If the user application interrupts routines use XRAM memory space: Save and
disable interrupts.
Load DPTR with the address to write
Store A register with the data to be written
Set bit EEE of EECON register
Execute a MOVX @DPTR, A
Clear bit EEE of EECON register
Restore interrupts.
EEBUSY flag in EECON is then set by hardware to indicate that programming is in
progress and that the EEPROM segment is not available for reading or writing.
The end of programming is indicated by a hardware clear of the EEBUSY flag.
4289A–8051–09/03
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