AT89C51ID2-SMSIM ATMEL [ATMEL Corporation], AT89C51ID2-SMSIM Datasheet - Page 119

• Manufacturer Part Number: AT89C51ID2-SMSIM
• Description: 8-bit Flash Microcontroller
• Manufacturer: ATMEL [ATMEL Corporation]

Default Values
Software Registers
4289A–8051–09/03
Table 88. Program Lock Bits
Note:
These security bits protect the code access through the parallel programming interface.
They are set by default to level 4. The code access through the ISP is still possible and
is controlled by the "software security bits" which are stored in the extra Flash memory
accessed by the ISP firmware.
To load a new application with the parallel programmer, a chip erase must first be done.
This will set the HSB in its inactive state and will erase the Flash memory. The part ref-
erence can always be read using Flash parallel programming modes.
The default value of the HSB provides parts ready to be programmed with ISP:
•
•
•
•
Several registers are used, in factory and by parallel programmers. These values are
used by Atmel ISP.
These registers are in the "Extra Flash Memory" part of the Flash memory. This block is
also called "XAF" or eXtra Array Flash. They are accessed in the following ways:
•
•
•
Several software registers described in Table 89.
Security
level
BLJB: Programmed force ISP operation.
X2: Unprogrammed to force X1 mode (Standard Mode).
XRAM: Unprogrammed to valid XRAM
LB2-0: Security level four to protect the code from a parallel access with maximum
security.
Commands issued by the parallel memory programmer.
Commands issued by the ISP software.
Calls of API issued by the application software.
1
2
3
4
Program Lock Bits
U: unprogrammed or "one" level.
P: programmed or "zero" level.
X: do not care
WARNING: Security level 2 and 3 should only be programmed after Flash and code
verification.
LB0
U
P
X
X
LB1
U
U
P
X
LB2
U
U
U
P
Protection description
No program lock features enabled.
MOVC instruction executed from external program memory is disabled
from fetching code bytes from internal memory, EA is sampled and
latched on reset, and further parallel programming of the on chip code
memory is disabled.
ISP and software programming with API are still allowed.
Writing EEprom Data from external parallel programmer is disabled but
still allowed from internal code execution.
Same as 2, also verify code memory through parallel programming
interface is disabled.
Writing And Reading EEPROM Data from external parallel programmer
is disabled but still allowed from internal code execution..
Same as 3, also external execution is disabled. (Default)
AT89C51ID2
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