AT89C51ID2-SMSIM ATMEL [ATMEL Corporation], AT89C51ID2-SMSIM Datasheet - Page 105

• Manufacturer Part Number: AT89C51ID2-SMSIM
• Description: 8-bit Flash Microcontroller
• Manufacturer: ATMEL [ATMEL Corporation]

Registers
Serial Peripheral Control
register (SPCON)
4289A–8051–09/03
Figure 43. SPI Interrupt Requests Generation
There are three registers in the module that provide control, status and data storage functions. These registers
are describes in the following paragraphs.
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Table 78 describes this register and explains the use of each bit.
Table 78. SPCON Register
SPCON - Serial Peripheral Control Register (0C3H)
Bit Number
SPR2
SPIF
MODF
SSDIS
The Serial Peripheral Control Register does the following:
Selects one of the Master clock rates,
Configure the SPI module as Master or Slave,
Selects serial clock polarity and phase,
Enables the SPI module,
Frees the SS pin for a general purpose
7
7
6
5
5
4
3
SPEN
6
Bit Mnemonic
SSDIS
MSTR
SPEN
CPOL
CPHA
SPR2
SPI Transmitter
CPU Interrupt Request
SSDIS
SPI Receiver/error
CPU Interrupt Request
5
Description
Serial Peripheral Rate 2
Bit with SPR1 and SPR0 define the clock rate.
Serial Peripheral Enable
Cleared to disable the SPI interface.
Set to enable the SPI interface.
SS Disable
Cleared to enable SS# in both Master and Slave modes.
Set to disable SS# in both Master and Slave modes. In Slave mode,
this bit has no effect if CPHA =’0’.
When SSDIS is set, no MODF interrupt request is generated.
Serial Peripheral Master
Cleared to configure the SPI as a Slave.
Set to configure the SPI as a Master.
Clock Polarity
Cleared to have the SCK set to’0’ in idle state.
Set to have the SCK set to’1’ in idle low.
Clock Phase
Cleared to have the data sampled when the SCK leaves the idle
state (see CPOL).
Set to have the data sampled when the SCK returns to idle state (see
CPOL).
MSTR
4
CPOL
3
CPU Interrupt Request
SPI
CPHA
2
AT89C51ID2
SPR1
1
SPR0
0
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