AT89C51ID2-SMSIM ATMEL [ATMEL Corporation], AT89C51ID2-SMSIM Datasheet - Page 102

• Manufacturer Part Number: AT89C51ID2-SMSIM
• Description: 8-bit Flash Microcontroller
• Manufacturer: ATMEL [ATMEL Corporation]

Master mode
Slave mode
Transmission Formats
102
AT89C51ID2
Figure 39. Full-Duplex Master-Slave Interconnection
The SPI operates in Master mode when the Master bit, MSTR
is set. Only one Master SPI device can initiate transmissions. Software begins the trans-
mission from a Master SPI module by writing to the Serial Peripheral Data Register
(SPDAT). If the shift register is empty, the byte is immediately transferred to the shift
register. The byte begins shifting out on MOSI pin under the control of the serial clock,
SCK. Simultaneously, another byte shifts in from the Slave on the Master’s MISO pin.
The transmission ends when the Serial Peripheral transfer data flag, SPIF, in SPSTA
becomes set. At the same time that SPIF becomes set, the received byte from the Slave
is transferred to the receive data register in SPDAT. Software clears SPIF by reading
the Serial Peripheral Status register (SPSTA) with the SPIF bit set, and then reading the
SPDAT.
The SPI operates in Slave mode when the Master bit, MSTR
cleared. Before a data transmission occurs, the Slave Select pin, SS, of the Slave
device must be set to’0’. SS must remain low until the transmission is complete.
In a Slave SPI module, data enters the shift register under the control of the SCK from
the Master SPI module. After a byte enters the shift register, it is immediately transferred
to the receive data register in SPDAT, and the SPIF bit is set. To prevent an overflow
condition, Slave software must then read the SPDAT before another byte enters the
shift register
least one bus cycle before the Master SPI starts a transmission. If the write to the data
register is late, the SPI transmits the data already in the shift register from the previous
transmission.
Software can select any of four combinations of serial clock (SCK) phase and polarity
using two bits in the SPCON: the Clock POLarity (CPOL
(CPHA
effect on the transmission format. CPHA defines the edges on which the input data are
sampled and the edges on which the output data are shifted (Figure 40 and Figure 41).
The clock phase and polarity should be identical for the Master SPI device and the com-
municating Slave device.
1.
2.
3.
4.
Clock Generator
SPI
4
Master MCU
). CPOL defines the default SCK line level in idle state. It has no significant
The SPI module should be configured as a Master before it is enabled (SPEN set). Also
The SPI module should be configured as a Slave before it is enabled (SPEN set).
The maximum frequency of the SCK for an SPI configured as a Slave is the bus clock
Before writing to the CPOL and CPHA bits, the SPI should be disabled (SPEN =’0’).
the Master SPI should be configured before the Slave SPI.
speed.
8-bit Shift register
(3)
. A Slave SPI must complete the write to the SPDAT (shift register) at
MOSI
SCK
SS
MISO
VDD
MOSI
MISO
SCK
VSS
SS
8-bit Shift register
Slave MCU
(2)
(4)
(1)
, in the SPCON register is
) and the Clock PHAse
, in the SPCON register
4289A–8051–09/03