STA014B STMICROELECTRONICS [STMicroelectronics], STA014B Datasheet
STA014B
Related parts for STA014B
STA014B Summary of contents
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... D/A converter, by the PCM Output Interface. This interface is software programmable to adapt the STA014 digital output 2 to the most common DACs architectures used on S the market. The functional STA014 chip partitioning is described in Fig.1a and Fig.1b. PRODUCT PREVIEW STA014T (TQFP44) STA014B (LFBGA 64) 1/45 ...
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... STA014-STA014B-STA014T Figure 1a. BLOCK DIAGRAM for TQFP44 and LFBGA64 package TQFP44 34 SDI SERIAL 36 SCKR INPUT INTERFACE 38 BIT_EN 27 BUFFER DATA-REQ 256 SCK_ADC ADC 26 LRCK_ADC INPUT INTERFACE 24 SDI_ADC 25 RESET Figure 1b. BLOCK DIAGRAM for SO28 package SO28 5 SDI SERIAL 6 SCKR INPUT INTERFACE 7 BIT_EN 28 BUFFER ...
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... F2 = SCKT D7 = TESTEN H1 = LRCKT A7 = SDI_ADC H3 = OCLK B6 = RESET F3 = VSS_2 A5 = LRCK_ADC C5 = OUT_CLK/DATA_REQ E4 = VDD_2 G4 = VSS_3 B5 = VDD_1 G5 = VDD_3 B4 = VSS_1 F5 = PVDD A4 = SDA G6 = PVSS B3 = SCL LFBGA64 STA014-STA014B-STA014T GPSO_DATA SCL SDA VSS_1 VDD_1 GPSO_SCKR OUT_CLK/DATA_REC LRCK_ADC RESET SDI_ADC N. GPIO_STROBE C3 = IODATA [ IODATA [ IODATA [ IODATA [ GPSO_REQ F8 = IODATA [3] ...
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... STA014-STA014B-STA014T 1. OVERVIEW 1.1 - MP3 decoder engine The MP3 decoder engine is able to decode any Layer III compliant bitstream: MPEG1, MPEG2 and MPEG2.5 streams are supported. Besides audio data decoding the MP3 engine also per- forms ANCILLARY data extraction: these data can be retrieved via I2C bus by the application microcontroller in order to implement specific functions ...
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... I/O GPIO Strobe Signal O GPSO Request Signal I GPSO Serial Clock O GPSO Serial Data STA014-STA014B-STA014T PAD Description CMOS Input Pad Buffer CMOS 4mA Output Drive CMOS Input Pad Buffer CMOS Input Pad Buffer CMOS Input Pad Buffer CMOS Input Pad Buffer with pull up ...
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... STA014-STA014B-STA014T 1. ELECTRICAL CHARACTERISTICS: V specified DC OPERATING CONDITIONS Symbol V Power Supply Voltage DD T Operating Junction Temperature j GENERAL INTERFACE ELECTRICAL CHARACTERISTICS Symbol Parameter I Low Level Input Current IL Without pull-up device I High Level Input Current IH Without pull-up device V Electrostatic Protection esd Note 1: The leakage currents are generally very small, < 1nA. The value given here is a maximum that can occur after an electrostatic stress on the pin ...
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... Output V DD SDA Other Outputs V REF D98AU967 Other frequencies may be supported upon re- quest to STMicroelectronics. Each frequency is supported by downloading a specific configura- tion file, provided by STM XTI is an input Pad with specific levels. Test Condition STA014-STA014B-STA014T SDA 3 SCL 4 SDO 9 SCKT 10 LRCKT 11 OCLK 12 SDI ...
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... STA014-STA014B-STA014T Figure 5. PLL and Clocks Generation System XTI 2.2 - PLL & Clock Generator System When STA014 receives the input clock, as de- scribed in Section 2.1, and a valid layer III input bitstream, the internal PLL locks, providing to the DSP Core the master clock (DCLK), and to the Audio Output Interface the nominal frequencies of the incoming compressed bit stream ...
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... P XTI XTO FILT IIC SCL SDA PLL IIC MPEG DECODER SERIAL AUDIO INTERFACE RX TX STA014-STA014B-STA014T MUTE Clock State PCM Output 0 Not Running 0 1 Running 0 PCM Clock State Decoding Output Not Running 0 No Running 0 No Running Decoded Yes ...
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... STA014-STA014B-STA014T Figure 8. Serial Input Interface Clocks SDI SCKR SCKR BIT_EN 3. INTERFACE DESCRIPTION 3.1 - Serial Input Interface STA014 receives the input data (MSB first) through the Serial Input Interface (Fig.7 serial communication interface connected to the SDI (Serial Data Input) and SCKR (Receiver Se- rial Clock) ...
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... C + Interrupt (SCL + SDA + DATA_REQ) GPSO I/F (GPSO_REQ + GPSO_DATA + GPSO_SCKR (polling) (SCL + SDA) ADC I/F MUX GPSO ENCOD ENGINE SERIAL RECEIVER D99AU1064 STA014-STA014B-STA014T D00AU1145 Description GPIO data line GPIO strobe line 2 C bus (with Available on package TQFP44 LFBGA64 SO28/TQFP44 LFBGA64 TQFP44 LFBGA64 ...
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... STA014-STA014B-STA014T The following 4 figures (fig. 12, 13, 14, 15) show the available connection diagrams as far as ADPCM encoding function. As shown in the fig- ures some configuration is not available in SO28 package. Figure 12. Input from BITSTREAM, Output from I2C SDI SCKR DATA_REQ SO28 MCU TQFP44 LFBGA64 BIT_EN ...
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... SUB-ADDR DATA ACK STOP ACK ACK DEV-ADDR DATA START RW ACK ACK DATA DATA ACK ACK DEV-ADDR DATA START RW STA014-STA014B-STA014T 2 C bus definition. ACK STOP ACK ACK DATA IN STOP D98AU825B NO ACK STOP NO ACK STOP ACK ACK NO ACK DATA DATA D98AU826A STOP ...
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... STA014-STA014B-STA014T 5.4 - READ OPERATION (see Fig. 17) 5.4.1 - Current byte address read The STA014 has an internal byte address counter. Each time a byte is written or read, this counter is incremented. For the current byte address read mode, follow- ing a START condition the master sends the de- vice address with the RW bit set to 1. ...
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... WOW_ENABLE $C4 196 WOW_SPK_MODE $C5 197 WOW_TRUEBASS $C6 198 WOW_ FOCUS Note: 1) The HEX_COD is the hexadecimal adress that the microcontroller has to generate to access the information. 2) RESERVED: register used for production test only, or for future use. STA014-STA014B-STA014T DESCRIPTION RESET R/W 0x00 R/W (1) 0x00 R/W (8) 0x00 R/W (8) 0x00 R/W (1) 0x00 R/W (8) ...
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... STA014-STA014B-STA014T 6.1 - STA014 REGISTERS DESCRIPTION The STA014 device includes 256 I this document, only the user-oriented registers are described. The undocumented registers are reserved. These registers must never be ac- cessed (in Read or in Write mode). The Read- Only registers must never be written. The following table describes the meaning of the ...
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... Hardware Reset: 0x01 MSB don’t care normal operation play The PLAY command is handled according to the state of the decoder, as described in section 2.5. PLAY only becomes active when the decoder is in DECODE mode. STA014-STA014B-STA014T LSB EC5 EC4 EC3 EC2 ...
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... STA014-STA014B-STA014T MUTE Address: 0x14 (20) Type: R/W Software Reset: 0x00 Hardware Reset: 0x00 MSB don’t care normal operation mute The MUTE command is handled according to the state of the decoder, as described in section 2.5. MUTE sets the clock running. DATA_REQ_ENABLE Address: 0x18 (24) ...
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... H17 H16 Layer in Layer III these two flags must be set always to "01". Protection_bit It equals "1" redundancy has been added LSB and "0" if redundancy has been added H10 H9 H8 STA014-STA014B-STA014T LSB MPEG 2 ...
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... STA014-STA014B-STA014T Bitrate_index indicates the bitrate (Kbit/sec) depending on the MPEG ID. bitrate index ’0000’ free ’0001’ 32 ’0010’ 40 ’0011’ 48 ’0100’ 56 ’0101’ 64 ’0110’ 80 ’0111’ 96 ’1000’ 112 ’1001’ 128 ’1010’ 160 ’1011’ 192 ’ ...
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... A decimal unit correspond to an attenuation step of 1 dB. STA014-STA014B-STA014T the maximum attenuation D97AU667 Description OUTPUT ATTENUATION NO ATTENUATION -1dB -2dB : -96dB Description OUTPUT ATTENUATION NO ATTENUATION -1dB -2dB : -96dB the maximum attenuation 21/ ...
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... STA014-STA014B-STA014T DRB Address: 0x49 (73) Type: R/W Software Reset: 0xFF Hardware Reset: 0xFF MSB DRB7 DRB6 DRB5 DRB4 DRB register is used to re-direct the Right Chan- nel on the Left mix both the Channels. ...
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... PD7 PD6 PF9 PF8 PCMDIVIDER is used to set the frequency ratio between the OCLK (Oversampling Clock for DACs), and the SCKT (Serial Audio Transmitter Clock). The relation is the following: STA014-STA014B-STA014T ADPCM_SF 0x02 8KHz 0x0A 16KHz 0x0E 32KHz ...
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... STA014-STA014B-STA014T The Oversampling Factor (O_FAC) is related to OCLK and SCKT by the following expression: 1) OCLK_freq = O_FAC * LRCKT_ Freq (DAC relation) 2) OCLK_ Freq = 2 * (1+PCM_DIV) * 32* LRCKT_Freq (when 16 bit PCM mode is used) 3) OCLK_ Freq = 2 * (1+PCM_DIV) * 64* LRCKT_Freq (when 32 bit PCM mode is used) 4) PCM_DIV = (O_FAC/64 bit mode ...
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... The PCM samples precision in STA014 can 18-20-24 bits. When STA014 operates in 16 (18-20-24) bits mode, the number of bits transmitted during a LRCKT period is 32 (64). STA014-STA014B-STA014T Description PCM order the LS bit is transmitted First PCM order the MS bit is transmitted First The word is right aligned The word is left aligned ...
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... STA014-STA014B-STA014T PCMCROSS Address: 0x56 (86) Type: R/W Software Reset: 0x00 Hardware Reset: 0x00 MSB The default configuration for this register is ’0x00’. MFSDF (X) Address: 0x61 (97) Type: R/W Software Reset: 0x07 Hardware Reset: 0x07 ...
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... The registers TREBLE_FREQUENCY-HIGH and TREBLE_FREQUENCY-LOW, logically concate- nated bit wide register, are used to select the frequency, in Hz, where the selected fre- quency is +12dB respect to the stop band. By setting these registers, the following rule must be kept: Treble_Freq < Fs/2 STA014-STA014B-STA014T LSB SV5 ...
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... STA014-STA014B-STA014T BASS_FREQUENCY_LOW Address: 0x79 (121) Software Reset: 0x00 Hardware Reset: 0x00 MSB BF7 BF6 BF5 BF4 BF3 BASS_FREQUENCY_HIGH Address: 0x7A (122) Software Reset: 0x00 Hardware Reset: 0x00 MSB BF15 BF14 BF13 BF12 BF11 BF10 The registers BASS_FREQUENCY_HIGH and ...
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... LSB The allowed Attenuation/Enhancement range [-18dB, +18dB]. BE2 BE1 BE0 LSB STA014-STA014B-STA014T ENHANCE/ATTENUATION 1.5dB step +18 +16.5 +15 +13 -13.5 -15 -16.5 -18 29/45 ...
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... STA014-STA014B-STA014T TONE_ATTEN Address: 0x7D (125) Type: RW Software Reset: 0x00 Hardware Reset: 0x00 MSB TA7 TA6 TA5 TA4 TA3 In the digital output audio, the full signal is achieved with attenuation. For this rea- MSB ...
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... MSB This register enable/disable the GPSO interface. Setting the GEN bit will enable the serial interface for ADPCM data retrieving. Reset GEN bit to dis- able GPSO interface. STA014-STA014B-STA014T AA1 AA0 ASM_EN AFM_EN ADPCM Frame Mode Enable ...
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... STA014-STA014B-STA014T GPSO_CONF Address: 0xBA (186) Type: R/W Software Reset: 0x00 Hardware Reset: 0x00 MSB GSP: GPSO clock polarity Using this bit the GPSO_SCKR polarity can be controlled. Clearing GSP bit data on GPSO_DATA line will be provided on the rising edge of GPSO_SCKR (sampling on falling edge) ...
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... Software Reset: 0x00 Hardware Reset: 0x00 MSB These bits specify the position of the sample word referred to the LRCK slot boundary. Bit AWP0 thru AWP4 must be programmed with the number of bits to ignore after the sample word. STA014-STA014B-STA014T GOSP ...
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... STA014-STA014B-STA014T WOW_ENABLE Address: 0xC3 (195) Type: R/W Software Reset: 0x00 Hardware Reset: 0x00 MSB This register enable (1) or disable (0) the WOW feature. WOW_SPK_MODE Address: 0xC4 (196) Type: R/W Software Reset: 0x00 Hardware Reset: 0x00 MSB Using this register it’s possible to select one of 3 ...
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... Pin numbers 14, 16, 18, 20, 35, 37, 39, 41 OUTPUT PIN Z D98AU904 IO INPUT PIN CAPACITANCE IO D98AU905 INPUT PIN Z D98AU906 Z INPUT PIN D98AU907 IO INPUT PIN CAPACITANCE IO D00AU1150 STA014-STA014B-STA014T MAX LOAD Z 100pF OUTPUT MAX PIN LOAD 5pF IO 100pF CAPACITANCE A 3.5pF CAPACITANCE A 3.5pF OUTPUT MAX PIN LOAD ...
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... STA014-STA014B-STA014T 5.4. TIMING DIAGRAMS 5.4.1. Audio DAC Interface a) OCLK in output. The audio PLL is used to clock the DAC OCLK (OUTPUT) SDO SCKT LRCLK tsdo = 3.5 + pad_timing (Cload_SDO) - pad_timing (Cload_ OCLK) tsckt = 4 + pad_timing (Cload_SCKT) - pad_timing (Cload_ OCLK) tlrckt = 3.5 + pad_timing (Cload_LRCCKT) - pad_timing (Cload_ OCLK) b) OCLK in input. OCLK (INPUT) ...
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... Note: In "multimedia" mode, the CLK_OUT pad is DATA_REQ. In that case, no timing is given between the XTI input and this pad _biten _biten t sckr_min_period t sckr_min_low t sckr_min_high IGNORED VALID IGNORED t t D98AU971A sdi_setup sdi_hold t t _biten _biten t sckr_min_period t sckr_min_low t sckr_min_high IGNORED VALID IGNORED t t D99AU1038 sdi_setup sdi_hold t t _src_hi _src_low STA014-STA014B-STA014T SCLK_POL=0 SCLK_POL=4 D98AU972 D98AU973 37/45 ...
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... STA014-STA014B-STA014T 5.4.5. RESET The Reset min duration (t_reset_low_min) is 100ns RESET 5.5. CONFIGURATION FLOW EXAMPLE set set set set set set set set set 38/45 t reset_low_min HW RESET PCM-DIVIDER PCM OUTPUT INTERFACE CONFIGURATION PCM-CONF. { PLL FRAC_441_H, PLL FRAC_441_L, PLL PLL FRAC_H, CONFIGURATION PLL FRAC_L } FOR: { 48, 44.1, 32 29, 22 ...
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... PLL Configuration Sequence For 14.31818MHz Input Clock 384 Oversapling Rathio REGISTER VALUE ADDRESS 110 101 160 82 152 100 186 81 161 5 STA014-STA014B-STA014T NAME VALUE reserved 12 reserved 3 MFSDF (x) 15 MFSDF-441 16 PLLFRAC-H 187 PLLFRAC-441-H 103 PLLFRAC-L 58 PLLFRAC-441-L 119 PLLCTRL 161 NAME VALUE reserved ...
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... STA014-STA014B-STA014T Table 9: PLL Configuration Sequence For 14.31818MHz Input Clock 512 Oversapling Rathio REGISTER NAME ADDRESS 6 reserved 11 reserved 97 MFSDF (x) 80 MFSDF-441 101 PLLFRAC-H 82 PLLFRAC-441-H 100 PLLFRAC-L 81 PLLFRAC-441-L 5 PLLCTRL Table 10: PLL Configuration Sequence For 14.7456MHz Input Clock 256 Oversapling Rathio REGISTER NAME ADDRESS ...
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... C SUB-ADDRESS D98AU976 /*set file pointer to first row */ 2 /* generate I C start condition for STA014 device address */ /* write STA014 device address /* write data 2 /* generate I C stop condition /* update pointer to new file row /* repeat until End of File /* End routine STA014-STA014B-STA014T C command data (value 41/45 ...
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... STA014-STA014B-STA014T mm DIM. MIN. TYP. MAX. MIN. A 2.65 a1 0.1 0.3 0.004 b 0.35 0.49 0.014 b1 0.23 0.32 0.009 C 0 (typ.) D 17.7 18.1 0.697 E 10 10.65 0.394 e 1.27 e3 16.51 F 7.4 7.6 0.291 L 0.4 1.27 0.016 S 8 (max.) 42/45 inch MECHANICAL DATA TYP. MAX. 0.104 0.012 0.019 0.013 0.020 0.713 0.419 0.050 0.65 0.299 0.050 OUTLINE AND SO28 ...
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... inch TYP. MAX. MECHANICAL DATA 0.063 0.006 0.055 0.057 0.014 0.018 0.008 0.472 0.394 0.315 0.031 0.472 0.394 0.315 0.024 0.030 0.039 TQFP44 ( TQFP4410 STA014-STA014B-STA014T OUTLINE AND 0.10mm .004 Seating Plane C K 43/45 ...
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... STA014-STA014B-STA014T mm DIM. MIN. TYP. MAX. MIN. A 1.700 A1 0.350 0.400 0.450 0.014 A2 1.100 b 0.500 D 8.000 D1 5.600 e 0.800 E 8.000 E1 5.600 f 1.200 BALL 1 IDENTIFICATION (64 PLACES) e 44/45 inch TYP. MAX. 0.067 0.016 0.018 0.043 0.20 0.315 0.220 0.031 Body ...
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