STA014B STMICROELECTRONICS [STMicroelectronics], STA014B Datasheet - Page 8

• Manufacturer Part Number: STA014B
• Description: MPEG 2.5 LAYER III AUDIO DECODER WITH ADPCM AND SRS WOWO POSTPROCESSING CAPABILITY
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

STA014-STA014B-STA014T
Figure 5. PLL and Clocks Generation System
2.2 - PLL & Clock Generator System
When STA014 receives the input clock, as de-
scribed in Section 2.1, and a valid layer III input
bitstream, the internal PLL locks, providing to the
DSP Core the master clock (DCLK), and to the
Audio Output Interface the nominal frequencies of
the incoming compressed bit stream. The STA014
PLL block diagram is described in Figure 5.
The audio sample rates are obtained dividing the
oversampling clock (OCLK) by software programma-
ble factors. The operation is done by STA014 em-
bedded software and it is transparent to the user.
The STA014 PLL can drive directly most of the com-
mercial DACs families, providing an over sampling
clock, OCLK, obtained dividing the VCO frequency
with a software programmable dividers.
2.3 - STA014 Operational Modes
The device can be configured in 4 different op-
erational modes. To select one specific mode a
dedicated CHIP_MODE registers is available. For
proper operation the following steps must be is-
sued to switch between different modes:
- issue a software reset (SOFT_RESET register)
- select the desired mode (CHIP_MODE register)
- run the device (RUN register)
Hereby is a short description of each available
mode
8/45
ADPCM Encoder
This mode can be used to encode the incom-
ing bitstream with 4 different compression al-
gorithms. Moreover different sample frequen-
cies and word size are supported. For a
detailed description of this features refer to the
related registers.
ADPCM Decoder
This mode can be used when an ADPCM
compressed bitstream must be decoded.
XTI
Update FRAC
FRAC
N
Switching
Circuit
M
PFD
VCO
CP
Disable PLL
The input interface handling and control flow is
the same as in the MP3 Mode.
Using this mode it’s possible to use the em-
bedded post-processing controls (volume and
tone controls) to process an incoming uncom-
pressed stereo audio stream. In this configura-
tion ADC input is the only supported interface.
This could be useful, for instance, to process
audio data coming from an external tuner or
some other auxiliary source.
In MP3 Mode (default mode) STA014 decodes
the incoming bitstream, acting as a master of
the data communication from the source to it-
self.
This control is done by a specific buffer man-
agement, controlled by STA014 embedded
software. The data coming from the serial in-
terface are stored in the input buffer, a 256
bytes long FIFO.
The feedback line DATA_REQ actually is the
result of the h/w comparison between the writ-
ing address of the FIFO and the constant
value 252. This means that if the buffer is filled
up with more than 252 bytes the DATA_REQ
line goes low, requesting MCU to stop trans-
mission: the maximum time to stop transmit-
ting is given by the time required to transmit 4
bytes (this time, in turn, depends on the bit-
stream speed used to send MP3 data).
The input interface can receive data with a
speed up to 20Mbit/s. The speed at which the
FIFO is emptied is equal to the MP3 nominal
bitrate. Provided the FIFO is filled up with 252
bytes the time required to empty it (in worst
condition, which is 320kbit/s mpeg stream) is
about 6ms. So if no more data is received in
this time the buffer will be emptied and this will
badly affect the output audio.
BYPASS mode
MP3 mode
XTI2OCLK
XTI2DSPCLK
X
S
C
R
C
OCLK
DCLK