ADUC702X_1 AD [Analog Devices], ADUC702X_1 Datasheet - Page 21

• Manufacturer Part Number: ADUC702X_1
• Description: Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI MCU
• Manufacturer: AD [Analog Devices]

Preliminary Technical Data
Memory Access
The ARM7 core sees memory as a linear array of 2 32 byte
location where the different blocks of memory are mapped as
outlined in
Figure 4
The ADuC702x memory organisation is configured in little
endian format: the least significant byte is located in the lowest
byte address and the most significant byte in the highest byte
address.
Flash/EE Memory
The total 64kBytes of Flash/EE are organised as 32k X 16 bits.
31k X 16 bits are user space and 1k X 16 bits is reserved for boot
loader. The page size of this Flash/EE memory is 256Bytes.
62kBytes of Flash/EE are available to the user as code and non-
volatile data memory. There is no distinction between data and
program as ARM code shares the same space. The real width of
the Flash/EE memory is 16 bits, which means that in ARM
mode (32-bit instruction), two accesses to the Flash/EE are
necessary
recommended to use Thumb mode when executing from
Flash/EE memory for optimum access speed. The maximum
access speed for the Flash/EE memory is 45MHz in Thumb
mode and 22.5MHz in full ARM mode. More details on
Flash/EE access time are outlined later in ‘Execution from
SRAM and Flash/EE’ section of this datasheet.
SRAM
8kBytes of SRAM are available to the user, organized as 2k X 32
bits, i.e. 2kWords. ARM code can run directly from SRAM at
45MHz , given that the SRAM array is configured as a 32-bit
wide memory array. More details on SRAM access time are
outlined later in ‘Execution from SRAM and Flash/EE’ section
of this datasheet.
Memory Mapped Registers
The Memory Mapped Register (MMR) space is mapped into
the upper 2 pages of the Flash/EE space and accessed by
indirect addressing through the ARM7 banked registers.
.
bit31
Byte3
for each instruction fetch. It is therefore
B
7
3
Byte2
A
6
2
Figure 5: little endian format
32 bits
Byte1
9
5
1
Byte0
8
4
0
bit0
0xFFFFFFFFh
0x00000004h
0x00000000h
Rev. PrA | Page 21 of 78
The MMR space provides an interface between the CPU and all
on-chip peripherals. All registers except the core registers
reside in the MMR area. All shaded locations shown in Figure 6
are unoccupied or reserved locations and should not be
accessed by user software. Table 6 shows a full MMR memory
map.
0xFFFFFC3C
0xFFFFFFFF
0xFFFFFC00
0xFFFFF46C
0xFFFF0B54
0xFFFF0B00
0xFFFF0A14
0xFFFF0A00
0xFFFF048C
0xFFFFF820
0xFFFFF800
0xFFFFF400
0xFFFF0948
0xFFFF0900
0xFFFF0848
0xFFFF0800
0xFFFF0730
0xFFFF0700
0xFFFF0620
0xFFFF0600
0xFFFF0538
0xFFFF0500
0xFFFF0490
0xFFFF0448
0xFFFF0440
0xFFFF0420
0xFFFF0404
0xFFFF0370
0xFFFF0360
0xFFFF0350
0xFFFF0340
0xFFFF0334
0xFFFF0320
0xFFFF0310
0xFFFF0300
0xFFFF0238
0xFFFF0220
0xFFFF0110
0xFFFF0000
Figure 6: Memory Mapped
Oscillator Control
General Purpose
System Control
Power Supply
Flash Control
Reference
Watchdog
Controller
Remap &
Bandgap
Wake Up
Interface
Interrupt
Timer 0
Monitor
UART
PLL &
GPIO
Timer
Timer
Timer
PWM
I
I
DAC
ADC
PLA
SPI
ADuC702x Series
2
2
C1
C0