ADUC702X_1 AD [Analog Devices], ADUC702X_1 Datasheet - Page 48

• Manufacturer Part Number: ADUC702X_1
• Description: Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI MCU
• Manufacturer: AD [Analog Devices]

ADuC702x Series
GENERAL PURPOSE I/O
The ADuC702x provides 40 General Purpose bi-directional I/O
pins (GPIO). All I/O pins are 5V tolerant which means that the
GPIOs support an input voltage of 5V. In general many of the
GPIO pins have multiple functions, see Table 30 for the pin
function definition. By default the GPIO pins are configured in
GPIO mode. All GPIO pins have internal pull up resistor and
their drive capability is 2mA. The drive capability of P0.7 is
12mA.
The 30 GPIO are grouped in 5 ports, port 0 to 4. Each port is
controlled by four MMRs:
- GPxCON: Port x Control Register, selects the function of
- GPxDAT: Port x Configuration and Data Register. It
- GPxSET: data set port x
- GPxCLR: data clear port x
With x representing the port number.
See Table 6 page 3 for address location of these 20 registers.
The default value of GPxCON is 0x00000000, all port pins are
defined as GPIO, except GP0CON which is 0x01001000 in
order to make the TRST and MRST functions available at reset.
Bit
31-30
29-28
27-26
25-24
23-22
21-20
19-18
17-16
15-14
13-12
11-10
9-8
7-6
5-4
3-2
1-0
each pin of port x. as described in Table 29
configures the direction of the GPIO pins of port x, sets the
output value for the pins configured as output and receives
the stores the input value of the pins configured as input.
Table 29: GPxCON MMR Bit Descriptions
Description
Reserved
Select function of Px.7 pin
Reserved
Select function of Px.6 pin
Reserved
Select function of Px.5 pin
Reserved
Select function of Px.4 pin
Reserved
Select function of Px.3 pin
Reserved
Select function of Px.2 pin
Reserved
Select function of Px.1 pin
Reserved
Select function of Px.0 pin
Rev. PrA | Page 48 of 78
Port
0
1
2
3
4
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6
P4.7
Table 30: GPIO pin function Descriptions
Pin
Preliminary Technical Data
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
IRQ0
IRQ1
00
PWMSYNC
PWMTRIP
PWMTRIP
PWM0H
PWM1H
PWM2H
ADC
PWM0L
PWM1L
PWM2L
CONVS
MRST
SOUT
ECLK
TRST
DCD
CMP
DTR
CTS
DSR
RTS
SIN
01
RI
Configuration
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
BUSY
SOUT
MISO
MOSI
SDA0
SDA1
AD10
AD11
AD12
AD13
AD14
AD15
SCL0
SCL1
BHE
CLK
MS0
MS1
MS2
MS3
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
BLE
A16
SIN
CSL
WS
AE
AE
RS
10
-
-
-
PLAO[10]
PLAO[11]
PLAO[12]
PLAO[13]
PLAO[14]
PLAO[15]
PLAI[10]
PLAI[11]
PLAI[12]
PLAI[13]
PLAI[14]
PLAI[15]
PLAO[1]
PLAO[2]
PLAO[3]
PLAO[4]
PLAO[0]
PLAO[5]
PLAO[8]
PLAO[9]
ADC
PLAI[7]
PLAI[0]
PLAI[1]
PLAI[2]
PLAI[3]
PLAI[4]
PLAI[5]
PLAI[6]
PLAI[8]
PLAI[9]
11
-
-
-
-
-
-
-
-
-
BUSY