ADUC702X_1 AD [Analog Devices], ADUC702X_1 Datasheet - Page 32

• Manufacturer Part Number: ADUC702X_1
• Description: Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI MCU
• Manufacturer: AD [Analog Devices]

ADuC702x Series
FLASH/EE CONTROL INTERFACE
Serial, parallel and JTAG programming use the Flash/EE
Control Interface, which includes seven MMRs:
- FEESTA: read only register, reflects the status of the Flash
- FEEMOD: sets the operating mode of the Flash Control
- FEECON: 8-bit command register. The commands are
Bit
15-6
5
4
3
2
1
0
Bit
7-5
4
3-0
Code
0x00
0x01*
0x02*
0x03*
0x04*
0x05*
Control Interface
Interface
described Table 14
*
Description
Reserved
Burst command enable
Set when the command is a burst command: 0x07, 0x08 or 0x09
Cleared when other command
Reserved
Flash interrupt status bit
Set automatically when an interrupt occurs, i.e. when a command is complete and the Flash/EE interrupt enable bit in the
FEEMOD register is set
Cleared when reading FEESTA register
Flash/EE controller busy
Set automatically when the controller is busy
Cleared automatically when the controller is not busy
Command fail
Set automatically when a command completes unsuccessfully
Cleared automatically when reading FEESTA register
Command complete
Set by MicroConverter when a command is complete
Cleared automatically when reading FEESTA register
Description
Reserved
Flash/EE interrupt enable:
Set by user to enable the Flash/EE interrupt. The interrupt will occur when a command is complete.
Cleared by user to disable the Flash/EE interrupt
Reserved
command
Null
Single Read
Single Write
Erase-Write
Single Verify
Single Erase
Description
Idle state
Load FEEDAT with the 16-bit data indexed by FEEADR
Write FEEDAT at the address pointed by FEEADR. This operation takes 20µs.
Erase the page indexed by FEEADR and write FEEDAT at the location pointed by FEEADR. This operation
takes 20ms
Compare the contents of the location pointed by FEEADR to the data in FEEDAT. The result of the
comparison is returned in FEESTA bit 1
Erase the page indexed by FEEADR
Table 13: FEEMOD MMR bit designations
Table 12: FEESTA MMR bit designations
Table 14: command codes in FEECON
Rev. PrA | Page 32 of 78
- FEEDAT: 16-bit data register.
- FEEADR: 16-bit address register.
- FEESIGN: 24-bit code signature
- FEEPRO: protection following subsequent reset MMR.
- FEEHIDE: Immediate Protection MMR. Does not require
Requires software key. See description Table 15
any software keys. See description Table 15
Preliminary Technical Data