SAK-XC2264-56F66L INFINEON [Infineon Technologies AG], SAK-XC2264-56F66L Datasheet - Page 84

• Manufacturer Part Number: SAK-XC2264-56F66L
• Description: 16/32-Bit Single-Chip Microcontroller with 32-Bit Performance
• Manufacturer: INFINEON [Infineon Technologies AG]

Preliminary
The specification of the external timing (AC Characteristics) depends on the period of the
system clock (TCS).
Direct Drive
When direct drive operation is configured (SYSCON0.CLKSEL = 11
is derived directly from the input clock signal DIRIN:
f
The frequency of
time of
A similar configuration can be achieved by selecting the XTAL1
Prescaler Operation
When prescaler operation is configured (SYSCON0.CLKSEL = 10
= 1
XTAL1) or from the internal oscillator through the output-prescaler:
f
If the divider factor is selected as 1, the frequency of
of
clock
The lowest system clock frequency can be achieved in this mode by selecting the
maximum value for divider factor K1:
f
Phase Locked Loop (PLL)
When PLL operation is configured (SYSCON0.CLKSEL = 10
the on-chip phase locked loop provides the system clock. The PLL multiplies the
selected input frequency by the factor F (
divider (P), the multiplication factor (N), and the output divider (K2): (F = N+1 / (P+1 ×
K2+1)).
The input clock can be derived either from an external source via XTAL1 or from the on-
chip oscillator.
The PLL circuit synchronizes the system clock to the input clock. This synchronization is
done smoothly, i.e. the system clock frequency does not change abruptly.
Due to this adaptation to the input clock the frequency of
is locked to
of individual TCSs.
1) Voltages on XTAL1 must comply to the core supply voltage
Data Sheet
SYS
SYS
SYS
f
OSC
B
=
), the system clock is derived either from the crystal oscillator (input clock signal
=
=
f
f
f
f
. In this case, the high and low time of
OSC
IN
OSC
OSC
f
SYS
.
(external or internal).
/ (K1DIV + 1).
/ 1024.
is defined by the duty cycle of the input clock
f
IN
. The slight variation causes a jitter of
f
SYS
directly follows the frequency of
82
f
SYS
f
SYS
=
is defined by the duty cycle of the input
V
f
IN
DDI1
f
× F), which results from the input
SYS
.
f
SYS
f
IN
XC2000 Family Derivatives
. In this case, the high and low
f
which also affects the duration
f
SYS
IN
directly follows the frequency
.
B
is constantly adjusted so it
, PLLCON0.VCOBY = 0
1)
Electrical Parameters
input.
B
XC2267 / XC2264
, PLLCON0.VCOBY
B
), the system clock
V0.1, 2007-02
Draft Version
B
),