TDA6650ATT NXP [NXP Semiconductors], TDA6650ATT Datasheet - Page 8

• Manufacturer Part Number: TDA6650ATT
• Description: 5 V mixer/oscillator and low noise PLL synthesizer for hybrid terrestrial tuner (digital and analog)
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
8. I
TDA6650ATT_6651ATT_2
Product data sheet
2
C-bus protocol
8.1 Write mode; R/W = 0
Linked to this noise improvement, some disturbances may become visible while they were
not visible because they were hidden into the noise in analog dedicated applications and
circuits.
This is especially true for disturbances coming from the I
is intended for the MOPLL or for another slave on the bus.
To avoid this I
to use a bus gate that enables the signal on the bus to drive the MOPLL only when the
communication is intended for the tuner part (such a kind of I
the NXP terrestrial channel decoders), and to avoid unnecessary repeated sending of the
same information.
The TDA6650ATT; TDA6651ATT is controlled via the two-wire I
there is one device address (7 bits) and the R/W bit for selecting read or write mode. To be
able to have more than one MOPLL in an I
is selected depending on the voltage applied to address selection pin AS (see
The TDA6650ATT; TDA6651ATT fulfils the fast mode I
I
is designed in such a way that the pins SCL and SDA can be connected to 5 V, 3.3 V
or to 2.5 V pulled-up I
Table
After the address transmission (first byte), data bytes can be sent to the device (see
Table
The I
device within one single transmission (address + 5 data bytes).
The TDA6650ATT; TDA6651ATT can also be partly programmed on the condition that the
first data byte following the address is byte 2 (divider byte 1) or byte 4 (control byte 1). The
first bit of the first data byte transmitted indicates whether byte 2 (first bit = 0) or byte 4
(first bit = 1) will follow. Until an I
data bytes can be entered without the need to re-address the device. The fractional
calculator is updated only at the end of the transmission (STOP condition). Each control
byte is loaded after the 8th clock pulse of the corresponding control byte. Main divider
data are valid only if no new I
computation period of 50 s.
Both DB1 and DB2 need to be sent to change the main divider ratio. If the value of the
ratio selection bits R2, R1 and R0 are changed, the bytes DB1 and DB2 have to be sent in
the same transmission.
2
C-bus specification, except for the timing as described in
2
5).
6). Five data bytes are needed to fully program the TDA6650ATT; TDA6651ATT.
C-bus transceiver has an auto-increment facility that permits programming the
2
C-bus crosstalk and be able to have a clean noise spectrum, it is necessary
2
Rev. 02 — 2 February 2007
C-bus lines, depending on the voltage applied to pin BVS (see
2
C-bus transmission is started (START condition) during the
2
TDA6650ATT; TDA6651ATT
C-bus STOP condition is sent by the controller, additional
5 V mixer/oscillator and low noise PLL synthesizer
2
C-bus system, one of four possible addresses
2
C-bus, according to the NXP
2
C-bus traffic, whatever this traffic
Figure
2
C-bus gate is included into
2
C-bus. For programming,
4. The I
© NXP B.V. 2007. All rights reserved.
2
C-bus interface
Table
8 of 54
8).