NAND04GW3B2AN1E STMICROELECTRONICS [STMicroelectronics], NAND04GW3B2AN1E Datasheet - Page 29

• Manufacturer Part Number: NAND04GW3B2AN1E
• Description: 4 Gbit, 8 Gbit, 2112 Byte/1056 Word Page 3V, NAND Flash Memories
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

NAND04GW3B2B, NAND08GW3B2A
6.8.5
6.8.6
Table 9.
1. Only valid for Cache operations, for other operations it is same as SR6.
2. Only valid for Cache Program operations, for other operations it is Don’t Care.
SR4, SR3, SR2
SR7
SR6
SR5
SR1
SR0
Bit
the Cache Program operation has failed to program the previous page (page N-1) correctly.
If SR1 is set to ‘0’ the operation has completed successfully.
The Cache Program Error bit is only valid during Cache Program operations, during other
operations it is Don’t Care.
Error Bit (SR0)
The Error bit is used to identify if any errors have been detected by the P/E/R Controller. The
Error Bit is set to ’1’ when a program or erase operation has failed to write the correct data to
the memory. If the Error Bit is set to ‘0’ the operation has completed successfully. The Error
Bit SR0, in a Cache Program operation, indicates a failure on Page N.
SR4, SR3 and SR2 are Reserved
Status Register Bits
Cache Program Error
Program/ Erase/ Read
Program/ Erase/ Read
Cache Program Error
Cache Ready/Busy
Write Protection
Generic Error
Controller
Controller
Reserved
Name
(1)
(2)
Logic Level
Don’t Care
‘1’
‘0’
‘1’
‘0’
'1'
'0'
'1'
'0'
'1'
'0'
'1'
'0'
'1'
'0'
Not Protected
Protected
P/E/R C inactive, device ready
P/E/R C active, device busy
Cache Register ready (Cache only)
Cache Register busy (Cache only)
P/E/R C inactive, device ready
P/E/R C active, device busy
Page N-1 failed in Cache Program operation
Page N-1 programmed successfully
Error – operation failed
No Error – operation successful
Page N failed in Cache Program operation
Page N programmed successfully
Definition
Device operations
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