NAND04GW3B2AN1E STMICROELECTRONICS [STMicroelectronics], NAND04GW3B2AN1E Datasheet - Page 45

• Manufacturer Part Number: NAND04GW3B2AN1E
• Description: 4 Gbit, 8 Gbit, 2112 Byte/1056 Word Page 3V, NAND Flash Memories
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

NAND04GW3B2B, NAND08GW3B2A
Table 21.
1. The time to Ready depends on the value of the pull-up resistor tied to the Ready/Busy pin. See
2. ES = Electronic Signature.
3.
4. During a Program/Erase Enable Operation, t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
WHWH
RHRL1
t
RHRL2
WHBH
VHWH
RHQZ
EHQX
WHBL
WHRL
EHQZ
RLRH
RLQV
VLWH
DZRL
ELQV
RLRL
Figure
During a Program/Erase Disable Operation, t
t
ADL
is the time from W rising edge during the final address cycle to W rising edge during the first data cycle.
35.
t
t
t
t
ADL
t
CRRH
t
WW
t
t
t
t
WHR
COH
t
AC Characteristics for Operations
CHZ
RHZ
CEA
REH
t
t
REA
t
WB
RC
t
RP
IR
R
(3)
(4)
Data Hi-Z to Read Enable Low
Chip Enable High to Output Hi-Z
Chip Enable Low to Output Valid
Read Enable High to
Read Enable Low
Chip Enable high to Output Hold
Read Enable Low to
Read Enable High
Read Enable Low to
Read Enable Low
Read Enable Low to
Output Valid
Write Enable High to
Ready/Busy High
Write Enable High to Ready/Busy Low
Write Enable High to Read Enable Low
Read Enable High hold time during Cache Read operation
Last Address latched to Data Loading Time during Program
operations
Write Protection time
Read Enable High to Output Hi-z
WW
WW
Read Enable High Hold time
Read Enable Pulse Width
Read Cycle time
Read Enable Access time
Read ES Access time
Read Busy time
is the delay from WP high to W High.
is the delay from WP Low to W High.
(1)
(continued)
(2)
Max
Max
Max
Max
Max
Max
Min
Min
Min
Min
Min
Min
Min
Min
Min
Figure
DC and AC parameters
33,
100
100
100
100
Figure 34
50
50
30
10
15
15
30
25
25
60
0
and
45/58
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
ns