M58LT256JSB8ZA6 STMICROELECTRONICS [STMicroelectronics], M58LT256JSB8ZA6 Datasheet - Page 45

• Manufacturer Part Number: M58LT256JSB8ZA6
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

M58LT256JST, M58LT256JSB
7.2.1
7.3
Synchronous Burst Read Suspend
A Synchronous Burst Read operation can be suspended, freeing the data bus for other
higher priority devices. It can be suspended during the initial access latency time (before
data is output) or after the device has output data. When the Synchronous Burst Read
operation is suspended, internal array sensing continues and any previously latched internal
data is retained. A burst sequence can be suspended and resumed as often as required as
long as the operating conditions of the device are met.
A Synchronous Burst Read operation is suspended when Chip Enable, E, is Low and the
current address has been latched (on a Latch Enable rising edge or on a valid clock edge).
The Clock signal is then halted at V
When Output Enable, G, becomes Low again and the Clock signal restarts, the
Synchronous Burst Read operation is resumed exactly where it stopped.
WAIT being gated by E, it will remain active and will not revert to high impedance when G
goes High. So if two or more devices are connected to the system’s READY signal, to
prevent bus contention the WAIT signal of the M58LT256JST/B should not be directly
connected to the system’s READY signal.
WAIT will revert to high-impedance when Chip Enable, E, goes High.
See
Read Suspend ac
Single Synchronous Read mode
Single Synchronous Read operations are similar to Synchronous Burst Read operations
except that the memory outputs the same data to the end of the operation.
Synchronous Single Reads are used to read the Electronic Signature, Status Register, CFI,
Block Protection Status, Configuration Register Status or Protection Register. When the
addressed bank is in Read CFI, Read Status Register or Read Electronic Signature mode,
the WAIT signal is asserted during the X-latency and at the end of a 4, 8 and 16 word burst.
It is only de-asserted when output data are valid.
See
Read ac
Table 23: Synchronous Read ac
Table 23: Synchronous Read ac
waveforms, for details.
waveforms, for details.
IH
characteristics, and
characteristics, and
or at V
IL
, and Output Enable, G, goes High.
Figure 13: Synchronous Burst
Figure 11: Synchronous Burst
Read modes
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