M58LT256JSB8ZA6 STMICROELECTRONICS [STMicroelectronics], M58LT256JSB8ZA6 Datasheet - Page 8

• Manufacturer Part Number: M58LT256JSB8ZA6
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Description
1
8/106
Description
The M58LT256JST/B are 256 Mbit (16 Mbit x 16) non-volatile Secure Flash memories. They
may be erased electrically at block level and programmed in-system on a word-by-word
basis using a 1.7 V to 2.0 V V
the input/output pins. An optional 9 V V
programming.
The devices feature an asymmetrical block architecture. The M58LT256JST/B have an array
of 259 blocks, and are divided into 16 Mbit banks. There are 16 banks each containing 16
main blocks of 64 Kwords, and one parameter bank containing 4 parameter blocks of 16
kwords and 15 main blocks of 64 kwords.
The Multiple Bank Architecture allows Dual Operations, while programming or erasing in
one bank, read operations are possible in other banks. Only one bank at a time is allowed to
be in program or erase mode. It is possible to perform burst reads that cross bank
boundaries. The bank architecture is summarized in
in
the M58LT256JST, and at the bottom for the M58LT256JSB.
Each block can be erased separately. Erase can be suspended, in order to perform a
program or read operation in any other block, and then resumed. Program can be
suspended to read data at any memory location except for the one being programmed, and
then resumed. Each block can be programmed and erased over 100,000 cycles using the
supply voltage V
to speed up programming.
Program and Erase commands are written to the Command Interface of the memory. An
internal Program/Erase Controller takes care of the timings necessary for program and
erase operations. The end of a program or erase operation can be detected and any error
conditions identified in the Status Register. The command set required to control the
memory is consistent with JEDEC standards.
The device supports Synchronous Burst Read and Asynchronous Read from all blocks of
the memory array; at Power-up the device is configured for Asynchronous Read. In
Synchronous Burst Read mode, data is output on each clock cycle at frequencies of up to
52 MHz. The Synchronous Burst Read operation can be suspended and resumed.
The device features an Automatic Standby mode. When the bus is inactive during
Asynchronous Read operations, the device automatically switches to the Automatic Standby
mode. In this condition the power consumption is reduced to the standby value and the
outputs are still driven.
The M58LT256JST/B features an instant, individual block protection scheme that allows any
block to be protected or unprotected with no latency, enabling instant code and data
protection. They can be protected individually preventing any accidental programming or
erasure. There is an additional hardware protection against program and erase. When
V
Power-up.
The device includes 17 Protection Registers and 2 Protection Register locks, one for the first
Protection Register and the other for the 16 One-Time-Programmable (OTP) Protection
Registers of 128 bits each. The first Protection Register is divided into two segments: a 64
bit segment containing a unique device number written by ST, and a 64 bit segment One-
PP
Figure
≤ V
PPLK
3. The Parameter Blocks are located at the top of the memory address space for
all blocks are protected against program or erase. All blocks are protected at
DD
. There is a Buffer Enhanced Factory programming command available
DD
supply for the circuitry and a 2.7 V to 3.6 V V
PP
power supply is provided to speed up factory
Table
2, and the memory map is shown
M58LT256JST, M58LT256JSB
DDQ
supply for