HYI39S512160AE-7.5 QIMONDA [Qimonda AG], HYI39S512160AE-7.5 Datasheet - Page 16

• Manufacturer Part Number: HYI39S512160AE-7.5
• Description: 512-Mbit Synchronous DRAM
• Manufacturer: QIMONDA [Qimonda AG]

1)
2) For proper power-up see the operation section of this data sheet.
3) AC timing tests for LV-TTL versions have
4) If clock rising time is longer than 1 ns, a time (t
5) Access time from clock
6) If
7) These parameter account for the number of clock cycles and depend on the operating frequency of the clock, as follows:
8) It is recommended to use two clock cycles between the last data-in and the precharge command in case of a write command without Auto-
9) When a Write command with Auto Precharge has been issued, a time of
Rev. 1.52, 2007-06
03292006-6Y91-0T2Z
Parameter
Write Cycle
Last Data Input to Precharge
(Write without Auto Precharge)
Last Data Input to Activate
(Write with Auto Precharge)
DQM Write Mask Latency
T
time is measured between
Specified
rate between 0.8 V and 2.0 V.
Data out hold time
the number of clock cycles = specified value of timing period (counted in fractions as a whole number)
Precharge. One clock cycle between the last data-in and the precharge command is also supported, but restricted to cycle times tCK
greater or equal the specified tWR value, where
be applied. For each of the terms, if not already an integer, round up to the next highest integer.
A
t
T
= 0 to 70 °C for HYB...,
is longer than 1 ns, a time (
t
AC
and
t
OH
t
oh
parameters are measured with a 50 pF only, without any resistive termination and with an input signal of 1V / ns edge
is 1.8 ns for PC133 components with no termination and 0 pF load.
t
ac
T
is 4.6 ns for PC133 components with no termination and 0 pF load,
V
A
IH
= -40 to 85 °C for i-temp part (HYI..);
and
t
T
- 1) ns has to be added to this parameter.
V
IL
. All AC measurements assume
V
IL
C L O C K
IN P U T
O U T P U T
= 0.4 V and
T
/2 - 0.5) ns has to be added to this parameter.
t
ck
t
IS
is equal to the actual system clock time.
1 .4 V
V
IH
= 2.4 V with the timing referenced to the 1.4 V crossover point. The transition
t
t
L Z
IH
t
A C
16
V
SS
1 .4 V
t
t
T
= 0 V,
C L
Symbol
t
t
t
= 1 ns with the AC output load circuit shown in figure below.
WR
DAL(min.)
DQW
t
DAL(min)
V
DD
t
t
C H
t
O H
has be fullfilled before the next Activate Command can
T
,
V
Measurement conditions for
t
t
A C
H Z
DDQ
2 .4 V
0 .4 V
= 3.3 V ± 0.3 V,
Min.
15
—
0
IO.vsd
PC133–333
t
1 .4 V
CK
HY[I/B]39S512[40/80/16]0A[E/T]
is equal to the actual system clock time.
–7.5
512-Mbit Synchronous DRAM
Max.
—
—
—
t
T
= 1 ns
Internet Data Sheet
ns
t
t
CK
CK
Unit
FIGURE 2
t
AC
Note
8)
9)
and
1)2)3)
t
OH