HYB3165165TL-50 SIEMENS [Siemens Semiconductor Group], HYB3165165TL-50 Datasheet - Page 12

• Manufacturer Part Number: HYB3165165TL-50
• Description: 4M x 16-Bit Dynamic RAM
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

Notes:
1) All voltages are referenced to VSS.
2) ICC1, ICC3, ICC4 and ICC6 and ICC7 depend on cycle rate.
3) ICC1 and ICC4 depend on output loading. Specified values are measured with the output open.
4) Address can be changed once or less while RAS = Vil.In the case of ICC4 it can be changed once or less
5) An initial pause of 100 s is required after power-up followed by 8 RAS-only-refresh cycles, before proper
6) AC measurements assume tT = 2 ns.
7) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Also, transition times are
8) Measured with the specified current load and 100 pF at Voh = 2.0 V and Vol = 0.8 V.
9) Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a
10) Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a
11) Either tRCH or tRRH must be satisfied for a read cycle.
12) tOFF (max.) and tOEZ (max.) define the time at which the outputs achieve the open-circuit condition and are
13) Either tDZC or tDZO must be satisfied.
14) Either tCDD or tODD must be satisfied.
15) tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data
16) These parameters are referenced to CAS leading edge in early write cycles and to WRITE leading edge in
17) When using Self Refresh mode, the following refresh operations must be performed to ensure proper DRAM
Semiconductor Group
Vih may overshoot to VV + 0.2V for pulse widths of < 4ns with 3.3V. Vil may undershoot to -2.0V for pulse width
If row addresses are being refresh in an evenly distributed manner over the refresh interval using CBR refresh
< 4.0 ns with 3.3V. Pulse width measured at 50% points with amplitude measured peak to DC reference.
during a Hyper page mode cycle ( thpc).
device operation is achieved. In case of using internal refresh counter, a minimum of 8 CAS-before-RAS
initialization cycles instead of 8 RAS cycles are required.
measured between VIH and VIL.
reference point only: If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by
tCAC.
reference point only: If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by
tAA.
not referenced to output voltage levels.
sheet as electrical characteristics only. If tWCS > tWCS (min.), the cycle is an early write cycle and the I/O pin
will remain open-circuit (high impedance) through the entire cycle; if tRWD > tRWD (min.), tCWD > tCWD
(min.), tAWD > tAWD (min.) and tCPWD > tCPWD (min.) , the cycle is a read-write cycle and I/O pins will
contain data read from the selected cells. If neither of the above sets of conditions is satisfied, the condition
of the I/O pins (at access time) is indeterminate.
Read-Modify-Write cycles.
operation:
cycles, then only one CBR cycle must be performed immediatly after exit from Self Refresh.
refresh interval, then a full set of row refreshed must be performed immediately before entry to and immediatey
after exit from Self Refresh
If row addresses are being refresh in any other manner (ROR - Distributed/Burst or CBR-Burst) over the
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HYB3164(5)165T(L)-50/-60
4M x 16 EDO-DRAM