HYB18H256321BF QIMONDA [Qimonda AG], HYB18H256321BF Datasheet - Page 11

• Manufacturer Part Number: HYB18H256321BF
• Description: 256-Mbit GDDR3 Graphics RAM GDDR3 Graphics RAM
• Manufacturer: QIMONDA [Qimonda AG]

3
3.1
Rev. 0.80, 2007-09
09132007-07EM-7OYI
Functional Description
Mode Register Set Command (MRS)
Mode Register Set Command
FIGURE 2
11
The Mode Register stores the data for controlling the
operation modes of the memory. It programs CAS latency,
test mode, DLL Reset , the value of the Write Latency and the
Burst length. The Mode Register must be written after power
up to operate the SGRAM. During a ModeRegister Set
command the address inputs are sampled and stored in the
Mode Register. The Mode Register content can only be set or
changed when the chip is in Idle state. For non-READ
commands following a Mode Register Set a delay of
must be met.
The Mode Register Bitmap is supported in two configurations.
The first configuration is intended to support the Mid-Range-
Speed application. The second configuration supports higher
clock cycles for CAS latency and is therefore prepared to
support high-speed application. The selected configuration is
defined by Bit0 of EMRS2.
Internet Data Sheet
HYB18H256321BF
256-Mbit GDDR3
t
MRD