HYB18H256321BF QIMONDA [Qimonda AG], HYB18H256321BF Datasheet - Page 15

• Manufacturer Part Number: HYB18H256321BF
• Description: 256-Mbit GDDR3 Graphics RAM GDDR3 Graphics RAM
• Manufacturer: QIMONDA [Qimonda AG]

The ON/OFF state of the DQ/DM receivers depends on the Write Latency. The dependence is given in
3.1.5
The normal operating mode is selected by issuing a Mode Register Set command with bit A7 set to zero and bits A0-A6 and
A8-A11 set to the desired value.
3.1.6
The normal operating mode is selected by issuing a Mode Register Set command with bit A8 set to zero and bits A0-A7 and
A9-A11 set to the desired values. A DLL Reset is initiated by issuing a Mode Register Set command with bit A8 set to one and
bits A0-A7 and A9-A11 set to the desired values. The GDDR3 Graphics RAM returns automatically in the normal mode of
operations once the DLL reset is completed.
Rev. 0.80, 2007-09
09132007-07EM-7OYI
WL
3-4
5-6-7
Test mode
DLL Reset
DQ/DM-Receivers
Receivers are always on
Receivers are off and will be switched on by Write command and will be switched off again after
WL+BL
15
ON/OFF mode of DQ/DM receivers
Internet Data Sheet
Table
HYB18H256321BF
256-Mbit GDDR3
TABLE 7
7.