HYB18H256321BF QIMONDA [Qimonda AG], HYB18H256321BF Datasheet - Page 3

• Manufacturer Part Number: HYB18H256321BF
• Description: 256-Mbit GDDR3 Graphics RAM GDDR3 Graphics RAM
• Manufacturer: QIMONDA [Qimonda AG]

1
This chapter lists all main features of the product family HYB18H256321BF and the ordering information.
1.1
• 2.0 V
• 2.0 V
• 1.8 V
• 1.8 V
• Organization: 2048K × 32 × 4 banks
• 4096 rows and 512 columns (128 burst start locations) per
• Differential clock inputs (CLK and CLK)
• CAS latencies of 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17
• Write latencies of 3, 4, 5, 6, 7
• Burst sequence with length of 4, 8.
• 4n pre fetch
• Short RAS to CAS timing for Writes
•
•
1) HYB: designator for memory components
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
Rev. 0.80, 2007-09
09132007-07EM-7OYI
Part Number
HYB18H256321BF–11/12/14
HYB18H256321BF–10
bank
t
t
RAS
WR
18H:
256: 256-Mbit density
32: Organization
B: Product revision
F: Lead- and Halogen-Free
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
programmable for Writes with Auto-Precharge
Lockout support
V
V
V
V
V
DDQ
DDQ
DD
DDQ
DD
= 1.8 V
core voltage HYB18H256321BF–10
core voltage HYB18H256321BF–11/12/14
1)
IO voltage HYB18H256321BF–10
IO voltage HYB18H256321BF–11/12/14
Overview
Features
Organisation
×32
3
• Data mask for write commands
• Single ended READ strobe (RDQS) per byte. RDQS edge-
• Single ended WRITE strobe (WDQS) per byte. WDQS
• DLL aligns RDQS and DQ transitions with Clock
• Programmable IO interface including on chip termination
• Autoprecharge option with concurrent auto precharge
• 4k Refresh (32ms)
• Autorefresh and Self Refresh
• PG–TFBGA–136 package (10mm × 14mm)
• Calibrated output drive. Active termination support
• RoHS Compliant Product
Clock (MHz)
1000/900/800/700
aligned with READ data
center-aligned with WRITE data
(ODT)
support
1)
Package
PG–TFBGA–136
Ordering Information
Internet Data Sheet
HYB18H256321BF
256-Mbit GDDR3
TABLE 1