CYD18S72V CYPRESS [Cypress Semiconductor], CYD18S72V Datasheet - Page 15

• Manufacturer Part Number: CYD18S72V
• Description: FLEx72 3.3V 64K/128K/256K x 72 Synchronous Dual-Port RAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-06069 Rev. *D
Switching Waveforms
Read Cycle
Notes:
28. OE is asynchronously controlled; all other inputs (excluding MRST and JTAG) are synchronous to the rising clock edge.
29. ADS = CNTEN = LOW, and MRST = CNTRST = CNT/MSK = HIGH.
30. The output is disabled (high-impedance state) by CE = V
31. Addresses do not have to be accessed sequentially since ADS = CNTEN = V
Master Reset
MRST
ALL
ADDRESS/
DATA
LINES
ALL
OTHER
INPUTS
TMS
CNTINT
INT
TDO
Numbers are for reference only.
ADDRESS
DATA
BE0–BE7
R/W
CLK
OUT
OE
[11, 28, 29, 30, 31]
CE
t
RSF
t
t
t
t
SB
SW
SA
SC
A
t
RS
n
(continued)
t
t
t
t
INACTIVE
RSS
t
HB
HW
HA
t
HC
CH2
1 Latency
t
RSR
t
CYC2
t
CKLZ
t
CL2
IH
PRELIMINARY
A
n+1
following the next rising edge of the clock.
ACTIVE
t
CD2
IL
with CNT/MSK = V
Q
A
n
n+2
IH
constantly loads the address on the rising edge of the CLK.
t
DC
Q
t
SC
n+1
t
OHZ
A
n+3
t
OLZ
t
CYD04S72V
CYD09S72V
CYD18S72V
HC
t
OE
Page 15 of 26
Q
n+2