CYD18S72V CYPRESS [Cypress Semiconductor], CYD18S72V Datasheet - Page 23

• Manufacturer Part Number: CYD18S72V
• Description: FLEx72 3.3V 64K/128K/256K x 72 Synchronous Dual-Port RAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-06069 Rev. *D
Mailbox Interrupt Timing
Table 7. Read / Write and Enable Operation (Any Port)
Notes:
52. CE
53. Address “1FFFF” is the mailbox location for R_Port.
54. L_Port is configured for Write operation, and R_Port is configured for Read operation.
55. At least one byte enable (B0 – B3) is required to be active during interrupt operations.
56. Interrupt flag is set with respect to the rising edge of the Write clock, and is reset with respect to the rising edge of the Read clock.
57. OE is an asynchronous input signal.
58. When CE changes state, deselection and Read happen after one cycle of latency.
59. CE
CLK
L_PORT
ADDRESS
INT
CLK
R_PORT
ADDRESS
R
L
R
OE
H
X
X
X
L
0
0
= OE = ADS = CNTEN = LOW; CE
= OE = LOW; CE
t
CH2
1
CLK
= R/W = HIGH.
t
X
CH2
t
[52,53,54,55,56]
CYC2
t
CYC2
t
CL2
t
t
3FFFF
SA
CL2
t
1
SA
= CNTRST = MRST = CNT/MSK = HIGH.
A
t
HA
m
Inputs
t
t
HA
CE
SINT
H
X
L
L
L
0
PRELIMINARY
A
n
A
m+1
[1,14,57,58,59]
CE
H
H
H
X
L
1
A
n+1
3FFFF
R/W
t
RINT
X
X
H
X
L
A
n+2
DQ
A
m+3
Outputs
High-Z
High-Z
High-Z
D
0
D
OUT
– DQ
IN
71
Deselected
Deselected
Write
Read
Outputs Disabled
CYD04S72V
CYD09S72V
CYD18S72V
A
n+3
A
Operation
m+4
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