CYD18S72V CYPRESS [Cypress Semiconductor], CYD18S72V Datasheet - Page 6

• Manufacturer Part Number: CYD18S72V
• Description: FLEx72 3.3V 64K/128K/256K x 72 Synchronous Dual-Port RAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-06069 Rev. *D
Table 3. Address Counter and Counter Mask Register Control Operation (Any Port)
Address Counter and Mask Register Operations
This section describes the features only apply to 4Mbit and
9Mbit devices, not to 18Mbit device. Each port have a
programmable burst address counter. The burst counter
contains three registers: a counter register, a mask register,
and a mirror register.
The counter register contains the address used to access the
RAM array. It is changed only by the Counter Load, Increment,
Counter Reset, and by master reset (MRST) operations.
The mask register value affects the Increment and Counter
Reset operations by preventing the corresponding bits of the
counter register from changing. It also affects the counter
interrupt output (CNTINT). The mask register is changed only
by the Mask Load and Mask Reset operations, and by the
MRST. The mask register defines the counting range of the
counter register. It divides the counter register into two
regions: zero or more “0s” in the most significant bits define
the masked region, one or more “1s” in the least significant bits
define the unmasked region. Bit 0 may also be “0,” masking
the least significant counter bit and causing the counter to
increment by two instead of one.
The mirror register is used to reload the counter register on
increment operations (see “retransmit,” below). It always
contains the value last loaded into the counter register, and is
changed only by the Counter Load, and Counter Reset opera-
tions, and by the MRST.
Table 3 summarizes the operation of these registers and the
required input control signals. The MRST control signal is
asynchronous. All the other control signals in Table 3
(CNT/MSK, CNTRST, ADS, CNTEN) are synchronized to the
port’s CLK. All these counter and mask operations are
independent of the port’s chip enable inputs (CE0 and CE1)
Note:
14. X” = “Don’t Care,” “H” = HIGH, “L” = LOW.
15. Counter operation and mask register operation is independent of chip enables.
CLK
X
MRST CNT/MSK CNTRST ADS CNTEN
H
H
H
H
H
H
H
H
H
L
X
H
H
H
H
H
L
L
L
L
X
H
H
H
H
H
H
H
L
L
H
H
H
X
X
L
L
X
L
L
PRELIMINARY
[16]
H
H
H
X
X
X
X
L
L
L
Master Reset
Counter Reset
Counter Load
Counter Readback Read out counter internal value on address
Counter Increment Internally increment address counter value.
Counter Hold
Mask Reset
Mask Load
Mask Readback
Reserved
Operation
Counter enable (CNTEN) inputs are provided to stall the
operation of the address input and utilize the internal address
generated by the internal counter for fast, interleaved memory
applications. A port’s burst counter is loaded when the port’s
address strobe (ADS) and CNTEN signals are LOW. When the
port’s CNTEN is asserted and the ADS is deasserted, the
address counter will increment on each LOW to HIGH
transition of that port’s clock signal. This will Read/Write one
word from/into each successive address location until CNTEN
is deasserted. The counter can address the entire memory
array, and will loop back to the start. Counter reset (CNTRST)
is used to reset the unmasked portion of the burst counter to
0s. A counter-mask register is used to control the counter
wrap.
Counter Reset Operation
All unmasked bits of the counter and mirror registers are reset
to “0.” All masked bits remain unchanged. A Mask Reset
followed by a Counter Reset will reset the counter and mirror
registers to 00000, as will master reset (MRST).
Counter Load Operation
The address counter and mirror registers are both loaded with
the address value presented at the address lines.
Counter Increment Operation
Once the address counter register is initially loaded with an
external address, the counter can internally increment the
address value, potentially addressing the entire memory array.
Only the unmasked bits of the counter register are incre-
mented. The corresponding bit in the mask register must be
a “1” for a counter bit to change. The counter register is incre-
mented by 1 if the least significant bit is unmasked, and by 2
if it is masked. If all unmasked bits are “1,” the next increment
Reset address counter to all 0s and mask
register to all 1s.
Reset counter unmasked portion to all 0s.
Load counter with external address value
presented on address lines.
lines.
Constantly hold the address value for
multiple clock cycles.
Reset mask register to all 1s.
Load mask register with value presented on
the address lines.
Read out mask register value on address
lines.
Operation undefined
[14,15 ]
Description
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