CYD18S72V CYPRESS [Cypress Semiconductor], CYD18S72V Datasheet - Page 20

• Manufacturer Part Number: CYD18S72V
• Description: FLEx72 3.3V 64K/128K/256K x 72 Synchronous Dual-Port RAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-06069 Rev. *D
Switching Waveforms
Notes:
40. CE
41. Address in output mode. Host must not be driving address bus after t
42. Address in input mode. Host can drive address bus after t
43. An * is the internal value of the address counter (or the mask register depending on the CNT/MSK level) being Read out on the address lines.
Readback State of Address Counter or Mask Register
EXTERNAL
ADDRESS
DATA
INTERNAL
ADDRESS
CNTEN
A
0
ADS
0
–A
CLK
OUT
= OE = BE0 – BE7 = LOW; CE
17
t
t
SCN
SAD
EXTERNAL
ADDRESS
t
SA
LOAD
Q
A
x-2
n
t
t
HAD
HCN
t
HA
t
CH2
t
CYC2
t
CL2
READBACK
(continued)
COUNTER
INTERNAL
ADDRESS
1
Q
= R/W = CNTRST = MRST = HIGH.
x-1
A
n
t
CD2
INCREMENT
PRELIMINARY
CKHZ
Q
n
t
t
CA2
.
CKHZ
or t
CKLZ
[40, 41, 42, 43]
CM2
in next clock cycle.
A
n+1
A
n*
t
CKLZ
A
n+2
Q
n+1
A
Q
n+3
n+2
CYD04S72V
CYD09S72V
CYD18S72V
Q
A
n+3
Page 20 of 26
n+4