CYD18S72V CYPRESS [Cypress Semiconductor], CYD18S72V Datasheet - Page 16

• Manufacturer Part Number: CYD18S72V
• Description: FLEx72 3.3V 64K/128K/256K x 72 Synchronous Dual-Port RAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-06069 Rev. *D
Switching Waveforms
Bank Select Read
Notes:
32. In this depth-expansion example, B1 represents Bank #1 and B2 is Bank #2; each bank consists of one Cypress FLEx72 device from this data sheet. ADDRESS
33.
34. Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals.
35. During “No Operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity.
36.
37. CE
ADDRESS
ADDRESS
Read-to-Write-to-Read (OE = LOW)
DATA
DATA
ADDRESS
DATA
= ADDRESS
completed (labelled as no operation). One clock cycle is required to three-state the I/O for the Write operation on the next rising edge of CLK.
DATA
ADS = CNTEN= BE0 – BE7 = OE = LOW; MRST = CNTRST = CNT/MSK = HIGH.
CE
OUT(B2)
0
OUT(B1)
CE
CE
0
CLK
R/W
= BE0 – BE7 = R/W = LOW; CE
OUT
= OE = BE0 – BE7 = LOW; CE
CE
CLK
(B1)
(B1)
(B2)
IN
(B2)
(B2)
t
t
t
SW
SC
SA
t
t
t
t
.
SA
SC
SA
SC
[32, 33]
A
n
A
A
t
0
0
CH2
t
CH2
t
(continued)
t
CYC2
t
t
HW
HC
HA
t
t
t
t
t
CYC2
HA
HC
HA
HC
1
1
= R/W = CNTRST = MRST = HIGH.
= CNTRST = MRST = CNT/MSK = HIGH. When R/W first switches low, since OE = LOW, the Write operation cannot be
t
CL2
t
CL2
[31, 34, 35, 36, 37]
READ
A
n+1
A
A
t
CD2
1
1
t
CD2
PRELIMINARY
t
SW
t
Q
SC
n
Q
A
t
0
SC
n+2
t
A
DC
A
2
2
t
t
DC
HC
t
HW
t
HC
t
CD2
NO OPERATION
A
n+2
Q
A
t
A
1
CKHZ
3
t
3
DC
t
t
CKLZ
CKHZ
t
CD2
t
SD
D
A
n+2
n+2
Q
A
A
t
HD
4
2
4
t
t
t
CKHZ
CD2
CKLZ
WRITE
CYD04S72V
CYD09S72V
CYD18S72V
Q
3
A
n+3
Page 16 of 26
A
A
5
t
5
CKLZ
t
t
CKHZ
CD2
(B1)
Q
4