HYB18T512800BF QIMONDA [Qimonda AG], HYB18T512800BF Datasheet - Page 30

• Manufacturer Part Number: HYB18T512800BF
• Description: 240-Pin Registered DDR2 SDRAM Modules
• Manufacturer: QIMONDA [Qimonda AG]

1)
2)
3) Definitions for
4) For two rank modules: All active current measurements in the same
5) For details and notes see the relevant Qimonda component data sheet
6)
Rev. 1.1, 2007-03
03292006-EO3M-LEK7
Parameter
Self-Refresh Current
CKE ≤ 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are FLOATING, Data
bus inputs are FLOATING.
All Bank Interleave Read Current
All banks are being interleaved at minimum
and address bus inputs are STABLE during DESELECTS.
Parameter
LOW
STABLE
FLOATING
SWITCHING
V
I
Mode
I
buffers can be disabled using an EMRS(1) (Extended Mode Register Command) by setting A12 bit to HIGH.
DD
DD1
DDQ
specifications are tested after the device is properly initialized and
,
I
= 1.8 V ± 0.1 V;
DD4R
and
I
I
DD
Description
V
Inputs are stable at a HIGH or LOW level
Inputs are
Inputs are changing between HIGH and LOW every other clock (once per 2 cycles) for address and control
signals, and inputs changing between HIGH and LOW every other data transfer (once per cycle) for DQ
signals not including mask or strobes
DD7
IN
see
current measurements are defined with the outputs disabled (
≤
V
V
Table 21
DD
IL(ac).MAX
= 1.8 V ± 0.1 V
V
I
DD6
REF
, HIGH is defined as
current values are guaranteed up to
=
V
DDQ
/2
t
RC
without violating
V
IN
≥
V
I
IH(ac).MIN
out
30
= 0 mA.
I
t
DD
RRD
I
DD
current mode. The other rank is in
T
parameter are specified with ODT disabled.
HYS72T[64/128/256]xxxHP–[25F/2.5/3/3S/3.7]–B
using a burst length of 4. Control
CASE
I
of 85 °C max.
OUT
= 0 mA). To achieve this on module level the output
240-Pin Registered DDR2 SDRAM
I
DD2P
Definitions for
Internet Data Sheet
Precharge Power-Down
Symbol Note
I
I
DD6
DD7
TABLE 21
1)2)3)4)5)
6)
I
DD