M58WR032FB60ZB6 STMICROELECTRONICS [STMicroelectronics], M58WR032FB60ZB6 Datasheet - Page 60

• Manufacturer Part Number: M58WR032FB60ZB6
• Description: 32 Mbit (2Mb x 16, Multiple Bank, Burst) 1.8V Supply Flash Memory
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

M58WR032FT, M58WR032FB
APPENDIX B. COMMON FLASH INTERFACE
The Common Flash Interface is a JEDEC ap-
proved, standardized data structure that can be
read from the Flash memory device. It allows a
system software to query the device to determine
various electrical and timing parameters, density
information and functions supported by the mem-
ory. The system can interface easily with the de-
vice, enabling the software to upgrade itself when
necessary.
When the Read CFI Query Command is issued
the device enters CFI Query mode and the data
structure is read from the memory. Tables 30, 31,
32, 33, 34, 35, 36, 37,
Table 30. Query Structure Overview
Note: The Flash memory display the CFI data structure when CFI Query command is issued. In this table are listed the main sub-sections
60/86
Offset
1Bh
00h
10h
27h
80h
P
A
detailed in Tables 31, 32,
Reserved
CFI Query Identification String
System Interface Information
Device Geometry Definition
Primary Algorithm-specific Extended Query table
Alternate Algorithm-specific Extended Query table
Security Code Area
33
38
Sub-section Name
and 34. Query data is always presented on the lowest order data outputs.
and
39
show the ad-
dresses used to retrieve the data. The Query data
is always presented on the lowest order data out-
puts (DQ0-DQ7), the other outputs (DQ8-DQ15)
are set to 0.
The CFI data structure also contains a security
area where a 64 bit unique security number is writ-
ten (see
Map). This area can be accessed only in Read
mode by the final user. It is impossible to change
the security number after it has been written by
ST. Issue a Read Array command to return to
Read mode.
Reserved for algorithm-specific information
Command set ID and algorithm data offset
Device timing & voltage information
Flash device layout
Additional information specific to the Primary
Algorithm (optional)
Additional information specific to the Alternate
Algorithm (optional)
Lock Protection Register
Unique device Number and
User Programmable OTP
Figure 5., Protection Register Memory
Description