M58WR032FB60ZB6 STMICROELECTRONICS [STMicroelectronics], M58WR032FB60ZB6 Datasheet - Page 7

• Manufacturer Part Number: M58WR032FB60ZB6
• Description: 32 Mbit (2Mb x 16, Multiple Bank, Burst) 1.8V Supply Flash Memory
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

SUMMARY DESCRIPTION
The M58WR032FT/B is a 32 Mbit (2 Mbit x16)
non-volatile Flash memory that may be erased
electrically at block level and programmed in-sys-
tem on a Word-by-Word basis using a 1.7V to 2V
V
V
12V V
customer programming.
The V
provide absolute protection against program or
erase.
The device features an asymmetrical block archi-
tecture. M58WR032FT/B has an array of 71
blocks, and is divided into 4 Mbit banks. There are
7 banks each containing 8 main blocks of 32
KWords, and one parameter bank containing 8 pa-
rameter blocks of 4 KWords and 7 main blocks of
32 KWords. The Multiple Bank Architecture allows
Dual Operations, while programming or erasing in
one bank, Read operations are possible in other
banks. Only one bank at a time is allowed to be in
Program or Erase mode. It is possible to perform
burst reads that cross bank boundaries. The bank
architecture is summarized in
memory maps are shown in
eter Blocks are located at the top of the memory
address space for the M58WR032FT and at the
bottom for the M58WR032FB.
Each block can be erased separately. Erase can
be suspended, in order to perform program in any
other block, and then resumed. Program can be
suspended to read data in any other block and
then resumed. Each block can be programmed
and erased over 100,000 cycles using the supply
voltage V
programming commands available to speed up
programming.
Program and Erase commands are written to the
Command Interface of the memory. An internal
Program/Erase Controller takes care of the tim-
ings necessary for program and erase operations.
The end of a program or erase operation can be
detected and any error conditions identified in the
Status Register. The command set required to
DD
DDQ
supply for the circuitry and a 1.7V to 2.24V
supply for the Input/Output pins. An optional
PP
PP
pin can also be used as a control pin to
power supply is provided to speed up
DD
. There are two Enhanced Factory
Figure 4.
Table
The Param-
2., and the
control the memory is consistent with JEDEC stan-
dards.
The device supports synchronous burst read and
asynchronous read from all blocks of the memory
array; at power-up the device is configured for
asynchronous read. In synchronous burst mode,
data is output on each clock cycle at frequencies
of up to 66MHz. The synchronous burst read oper-
ation can be suspended and resumed.
The device features an Automatic Standby mode.
When the bus is inactive during Asynchronous
Read operations, the device automatically switch-
es to the Automatic Standby mode. In this condi-
tion the power consumption is reduced to the
standby value I
The M58WR032FT/B features an instant, individu-
al block locking scheme that allows any block to be
locked or unlocked with no latency, enabling in-
stant code and data protection. All blocks have
three levels of protection. They can be locked and
locked-down individually preventing any acciden-
tal programming or erasure. There is an additional
hardware protection against program and erase.
When V
program or erase. All blocks are locked at Power-
Up.
The device includes a Protection Register to in-
crease the protection of a system’s design. The
Protection Register is divided into two segments:
a 64 bit segment containing a unique device num-
ber written by ST, and a 128 bit segment One-
Time-Programmable (OTP) by the user. The user
programmable segment can be permanently pro-
tected.
Memory Map.
The memory is offered in a VFBGA56, 7.7 x 9mm,
8x7 active ball array, 0.75 mm pitch package.
In addition to the standard version, the package is
also available in Lead-free version, in compliance
with JEDEC Std J-STD-020B, the ST ECOPACK
7191395 Specification, and the RoHS (Restriction
of Hazardous Substances) directive. All packages
are compliant with Lead-free soldering processes.
The memory is supplied with all the bits erased
(set to ’1’).
Figure 5.
PP
V
PPLK
M58WR032FT, M58WR032FB
DD4
shows the Protection Register
all blocks are protected against
and the outputs are still driven.
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