PIC24FJ32GB002-E/ML MICROCHIP [Microchip Technology], PIC24FJ32GB002-E/ML Datasheet - Page 185

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PIC24FJ32GB002-E/ML

Manufacturer Part Number
PIC24FJ32GB002-E/ML
Description
28/44-Pin, 16-Bit, Flash Microcontrollers with USB On-The-Go (OTG) and nanoWatt XLP Technology
Manufacturer
MICROCHIP [Microchip Technology]
Datasheet
REGISTER 16-1:
 2010 Microchip Technology Inc.
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
ACKDT: Acknowledge Data bit (When operating as I
Value that will be transmitted when the software initiates an Acknowledge sequence.
1 = Sends NACK during Acknowledge
0 = Sends ACK during Acknowledge
ACKEN: Acknowledge Sequence Enable bit
(When operating as I
1 = Initiates Acknowledge sequence on SDAx and SCLx pins and transmits ACKDT data bit. Hardware
0 = Acknowledge sequence not in progress
RCEN: Receive Enable bit (when operating as I
1 = Enables Receive mode for I
0 = Receives sequence not in progress
PEN: Stop Condition Enable bit (when operating as I
1 = Initiates Stop condition on SDAx and SCLx pins. Hardware clear at end of master Stop sequence.
0 = Stop condition not in progress
RSEN: Repeated Start Condition Enabled bit (when operating as I
1 = Initiates Repeated Start condition on SDAx and SCLx pins. Hardware clear at end of master
0 = Repeated Start condition not in progress
SEN: Start Condition Enabled bit (when operating as I
1 = Initiates Start condition on SDAx and SCLx pins. Hardware clear at end of master Start sequence.
0 = Start condition not in progress
clear at end of master Acknowledge sequence.
Repeated Start sequence
I2CxCON: I2Cx CONTROL REGISTER (CONTINUED)
2
C master. Applicable during master receive.)
2
C. Hardware clear at end of eighth bit of master receive data byte.
PIC24FJ64GB004 FAMILY
2
C master)
2
2
C master. Applicable during master receive.)
C master)
2
C master)
2
C master)
DS39940D-page 185

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