PIC24FJ32GB002-E/ML MICROCHIP [Microchip Technology], PIC24FJ32GB002-E/ML Datasheet - Page 232
![no-image](/images/no-image-200.jpg)
PIC24FJ32GB002-E/ML
Manufacturer Part Number
PIC24FJ32GB002-E/ML
Description
28/44-Pin, 16-Bit, Flash Microcontrollers with USB On-The-Go (OTG) and nanoWatt XLP Technology
Manufacturer
MICROCHIP [Microchip Technology]
Datasheet
1.PIC24FJ32GB002-EML.pdf
(352 pages)
- Current page: 232 of 352
- Download datasheet (3Mb)
PIC24FJ64GB004 FAMILY
REGISTER 19-1:
DS39940D-page 232
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12-11
bit 10
bit 9
bit 8
bit 7-6
bit 5
bit 4
bit 3
Note 1:
PMPEN
R/W-0
R/W-0
CSF1
2:
PMA<10:2> bits are not available on 28-pin devices.
These bits have no effect when their corresponding pins are used as address lines.
PMPEN: Parallel Master Port Enable bit
1 = PMP is enabled
0 = PMP is disabled, no off-chip access performed
Unimplemented: Read as ‘0’
PSIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
ADRMUX<1:0>: Address/Data Multiplexing Selection bits
11 = Reserved
10 = All 16 bits of address are multiplexed on PMD<7:0> pins
01 = Lower 8 bits of address are multiplexed on PMD<7:0> pins; upper 3 bits are multiplexed on
00 = Address and data appear on separate pins
PTBEEN: Byte Enable Port Enable bit (16-Bit Master mode)
1 = PMBE port is enabled
0 = PMBE port is disabled
PTWREN: Write Enable Strobe Port Enable bit
1 = PMWR/PMENB port is enabled
0 = PMWR/PMENB port is disabled
PTRDEN: Read/Write Strobe Port Enable bit
1 = PMRD/PMWR port is enabled
0 = PMRD/PMWR port is disabled
CSF<1:0>: Chip Select Function bits
11 = Reserved
10 = PMCS1 functions as chip set
01 = Reserved
00 = Reserved
ALP: Address Latch Polarity bit
1 = Active-high (PMALL and PMALH)
0 = Active-low (PMALL and PMALH)
Unimplemented: Read as ‘0’
CS1P: Chip Select 1 Polarity bit
1 = Active-high (PMCS1/PMCS1)
0 = Active-low (PMCS1/PMCS1)
R/W-0
CSF0
U-0
—
PMA<10:8>
PMCON: PARALLEL PORT CONTROL REGISTER
W = Writable bit
‘1’ = Bit is set
R/W-0
R/W-0
PSIDL
ALP
(2)
ADRMUX1
(2)
(2)
R/W-0
U-0
—
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
ADRMUX0
R/W-0
R/W-0
CS1P
(2)
(1)
(1)
PTBEEN
R/W-0
R/W-0
BEP
2010 Microchip Technology Inc.
x = Bit is unknown
PTWREN
WRSP
R/W-0
R/W-0
PTRDEN
R/W-0
R/W-0
RDSP
bit 8
bit 0
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