PIC24FJ32GB002-E/ML MICROCHIP [Microchip Technology], PIC24FJ32GB002-E/ML Datasheet - Page 57

• Manufacturer Part Number: PIC24FJ32GB002-E/ML
• Description: 28/44-Pin, 16-Bit, Flash Microcontrollers with USB On-The-Go (OTG) and nanoWatt XLP Technology
• Manufacturer: MICROCHIP [Microchip Technology]

REGISTER 5-1:
 2010 Microchip Technology Inc.
R/SO-0, HC
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12-7
bit 6
bit 5-4
bit 3-0
Note 1:
WR
U-0
—
2:
3:
These bits can only be reset on POR.
All other combinations of NVMOP<3:0> are unimplemented.
Available in ICSP™ mode only. Refer to the device programming specification.
(1)
WR: Write Control bit
1 = Initiate a Flash memory program or erase operation. The operation is self-timed and the bit is
0 = Program or erase operation is complete and inactive
WREN: Write Enable bit
1 = Enable Flash program/erase operations
0 = Inhibit Flash program/erase operations
WRERR: Write Sequence Error Flag bit
1 = An improper program or erase sequence attempt, or termination has occurred (bit is set
0 = The program or erase operation completed normally
Unimplemented: Read as ‘0’
ERASE: Erase/Program Enable bit
1 = Perform the erase operation specified by NVMOP<3:0> on the next WR command
0 = Perform the program operation specified by NVMOP<3:0> on the next WR command
Unimplemented: Read as ‘0’
NVMOP<3:0>: NVM Operation Select bits
1111 = Memory bulk erase operation (ERASE = 1) or no operation (ERASE = 0)
0011 = Memory word program operation (ERASE = 0) or no operation (ERASE = 1)
0010 = Memory page erase operation (ERASE = 1) or no operation (ERASE = 0)
0001 = Memory row program operation (ERASE = 0) or no operation (ERASE = 1)
R/W-0
R/W-0
ERASE
WREN
cleared by hardware once the operation is complete.
automatically on any set attempt of the WR bit)
NVMCON: FLASH MEMORY CONTROL REGISTER
(1)
(1)
SO = Settable Only bit
W = Writable bit
‘1’ = Bit is set
R/W-0, HS
WRERR
U-0
—
(1)
(1)
(1)
U-0
U-0
—
—
PIC24FJ64GB004 FAMILY
(1)
(1)
HC = Hardware Clearable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
NVMOP3
(1,2)
R/W-0
U-0
—
(1)
(2)
NVMOP2
R/W-0
U-0
—
(1)
(2)
HS = Hardware Settable bit
x = Bit is unknown
NVMOP1
R/W-0
U-0
—
(3)
(1)
(2)
DS39940D-page 57
NVMOP0
R/W-0
U-0
—
(1)
bit 8
bit 0
(2)