P89LPC980 NXP [NXP Semiconductors], P89LPC980 Datasheet - Page 39

• Manufacturer Part Number: P89LPC980
• Description: 8-bit microcontroller with accelerated two-clock 80C51 core, 4 kB/8 kB wide-voltage byte-erasable flash with 10-bit ADC
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
P89LPC980_982_983_985_2
Preliminary data sheet
7.16.1.1 Quasi-bidirectional output configuration
7.16.1.2 Open-drain output configuration
7.16.1 Port configurations
7.16 I/O ports
The P89LPC980/982/983/985 has four I/O ports: Port 0, Port 1, Port 2 and Port 3. Ports 0,
1, and 2 are 8-bit ports, and Port 3 is a 2-bit port. The exact number of I/O pins available
depends upon the clock and reset options chosen, as shown in
Table 9.
All but three I/O port pins on the P89LPC980/982/983/985 may be configured by software
to one of four types on a bit-by-bit basis. These are: quasi-bidirectional (standard 80C51
port outputs), push-pull, open drain, and input-only. Two configuration registers for each
port select the output type for each port pin.
Quasi-bidirectional output type can be used as both an input and output without the need
to reconfigure the port. This is possible because when the port outputs a logic HIGH, it is
weakly driven, allowing an external device to pull the pin LOW. When the pin is driven
LOW, it is driven strongly and able to sink a fairly large current. These features are
somewhat similar to an open-drain output except that there are three pull-up transistors in
the quasi-bidirectional output that serve different purposes.
A quasi-bidirectional port pin has a Schmitt trigger input that also has a glitch suppression
circuit.
The open-drain output configuration turns off all pull-ups and only drives the pull-down
transistor of the port driver when the port latch contains a logic 0. To be used as a logic
output, a port configured in this manner must have an external pull-up, typically a resistor
tied to V
An open-drain port pin has a Schmitt trigger input that also has a glitch suppression
circuit.
Clock source
On-chip oscillator or watchdog
oscillator
External clock input
Low/medium/high speed
oscillator (external crystal or
resonator)
1. P1.5 (RST) can only be an input and cannot be configured.
2. P1.2 (SCL/T0) and P1.3 (SDA/INT0) may only be configured to be either input-only or
open-drain.
DD
.
Number of I/O pins available
Rev. 02 — 8 February 2010
8-bit microcontroller with accelerated two-clock 80C51 core
Reset option
No external reset (except during
power-up)
External RST pin supported
No external reset (except during
power-up)
External RST pin supported
No external reset (except during
power-up)
External RST pin supported
P89LPC980/982/983/985
Table
9.
© NXP B.V. 2010. All rights reserved.
Number of I/O
pins (28-pin
package)
26
25
25
24
24
23
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