P89LPC980 NXP [NXP Semiconductors], P89LPC980 Datasheet - Page 50

• Manufacturer Part Number: P89LPC980
• Description: 8-bit microcontroller with accelerated two-clock 80C51 core, 4 kB/8 kB wide-voltage byte-erasable flash with 10-bit ADC
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
P89LPC980_982_983_985_2
Preliminary data sheet
Fig 14. SPI block diagram
SPI STATUS REGISTER
BY 4, 16, 64, 128
CPU clock
DIVIDER
SELECT
SPI CONTROL
7.24 SPI
The P89LPC980/982/983/985 provides another high-speed serial communication
interface: the SPI interface. SPI is a full-duplex, high-speed, synchronous communication
bus with two operation modes: Master mode and Slave mode. Up to 3 Mbit/s can be
supported in either Master mode or Slave mode. It has a Transfer Completion Flag and
Write Collision Flag Protection.
The SPI interface has four pins: SPICLK, MOSI, MISO and SS:
Typical connections are shown in
•
•
SPICLK, MOSI and MISO are typically tied together between two or more SPI
devices. Data flows from master to slave on MOSI (Master Out Slave In) pin and flows
from slave to master on MISO (Master In Slave Out) pin. The SPICLK signal is output
in the Master mode and is input in the Slave mode. If the SPI system is disabled, i.e.,
SPEN (SPCTL.6) = 0 (reset value), these pins are configured for port functions.
SS is the optional slave select pin. In a typical configuration, an SPI master asserts
one of its port pins to select one SPI device as the current slave. An SPI slave device
uses its SS pin to determine whether it is selected.
interrupt
request
SPI clock (master)
SPI
MSTR
SPEN
Rev. 02 — 8 February 2010
internal
data
bus
8-bit microcontroller with accelerated two-clock 80C51 core
SPI CONTROL REGISTER
8-BIT SHIFT REGISTER
READ DATA BUFFER
CLOCK LOGIC
Figure 15
P89LPC980/982/983/985
clock
through
Figure
17.
M
M
M
S
S
S
CONTROL
LOGIC
PIN
© NXP B.V. 2010. All rights reserved.
002aaa900
MISO
P2.3
MOSI
P2.2
SPICLK
P2.5
SS
P2.4
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