R5F21133DFP RENESAS [Renesas Technology Corp], R5F21133DFP Datasheet - Page 125

• Manufacturer Part Number: R5F21133DFP
• Description: 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY/R8C/Tiny SERIES
• Manufacturer: RENESAS [Renesas Technology Corp]

R8C/13 Group
Rev.1.20
REJ09B0111-0120
13.1 Clock Synchronous Serial I/O Mode
Table 13.1 Clock Synchronous Serial I/O Mode Specifications
NOTES:
1. When an external clock is selected, the conditions must be met while if the U0C0 register0 CKPOL bit =
2. If an overrun error occurs, the value of U0RB register will be indeterminate. The IR bit of S0RIC register
Interrupt request
generation timing
Transfer data format
Transfer clock
Transmission start condition
Reception start condition
Error detection
Select function
The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. This mode can
be selected with UART0. Table 13.1 lists the specifications of the clock synchronous serial I/O mode.
Table 13.2 lists the registers used in clock synchronous serial I/O mode and the register values set.
0 (transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer
clock), the external clock is in the high state; if the CKPOL bit in the U0C0 register is set to “1” (transmit
data output at the rising edge and the receive data taken in at the falling edge of the transfer clock), the
external clock is in the low state.
does not change.
Jan 27, 2006
Item
page 114 of 205
• Transfer data length: 8 bits
• CKDIR bit in U0MR register is set to “0” (internal clock): fi/(2(n+1))
• CKDIR bit is set to “1” (external clock ): input from CLK0 pin
• Before transmission can start, the following requirements must be met
_
_
• Before reception can start, the following requirements must be met
_
_
_
• For transmission, one of the following conditions can be selected
_
_
• For reception
• Overrun error
• CLK polarity selection
• LSB first, MSB first selection
• Continuous receive mode selection
When transferring data from the UART0 receive register to the U0RB register (at
completion of reception)
fi=f
data from UARTi transmit register
This error occurs if serial interface started receiving the next data before reading the
U0RB register and received the 7th bit of the next data
Transfer data I/O can be chosen to occur synchronously with the rising or
Whether to start sending/receiving data beginning with bit 0 or beginning with bit 7
can be selected
Reception is enabled immediately by reading the U0RB register
TE bit in U0C1 register is set to “1” (transmission enabled)
TI bit in U0C1 register is set to “0” (data present in U0TB register)
RE bit in U0C1 register is set to “1” (reception enabled)
TE bit in U0C1 register is set to “1” (transmission enabled)
TI bit in U0C1 register is set to “0” (data present in the U0TB register)
U0IRS bit is set to “0” (transmit buffer empty): when transferring data from
U0IRS bit is set to “1” (transfer completed): when serial interface finished sending
U0TB register to UART0 transmit register (at start of transmission)
the falling edge of the transfer clock
1SIO
, f
8SIO
, f
(2)
32SIO
n=setting value in UiBRG register: 00
Specification
13.1 Clock Synchronous Serial I/O Mode
16
to FF
(1)
16
(1)