R5F21133DFP RENESAS [Renesas Technology Corp], R5F21133DFP Datasheet - Page 67

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R5F21133DFP

Manufacturer Part Number
R5F21133DFP
Description
16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY/R8C/Tiny SERIES
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet

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Part Number:
R5F21133DFP#U0
Manufacturer:
Renesas Electronics America
Quantity:
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R8C/13 Group
Rev.1.20
REJ09B0111-0120
Figure 10.5 Interrupt Response Time
Table 10.5 IPL Level That Is Set to IPL When A Software or Special Interrupt Is Accepted
Watchdog timer, oscillation stop detection, voltage detection
Software, address match, single-step
• Variation of IPL when Interrupt Request is Accepted
• Interrupt Response Time
Jan 27, 2006
When a maskable interrupt request is accepted, the interrupt priority level of the accepted interrupt is
set in the IPL.
When a software interrupt or special interrupt request is accepted, one of the interrupt priority levels
listed in Table 10.5 is set in the IPL. Shown in Table 10.5 are the IPL values of software and special
interrupts when they are accepted.
Interrupt request generated
Figure 10.5 shows the interrupt response time. The interrupt response or interrupt acknowledge time
denotes a time from when an interrupt request is generated till when the first instruction in the inter-
rupt routine is executed. Specifically, it consists of a time from when an interrupt request is gener-
ated till when the instruction then executing is completed (see #a in Figure 10.5) and a time during
which the interrupt sequence is executed (20 cycles, see #b in Figure 10.5).
(a) A time from when an interrupt request is generated till when the instruction then
(b) 21 cycles for address match and single-step interrupts.
executing is completed. The length of this time varies with the instruction being
executed. The DIVX instruction requires the longest time, which is equal to 30 cycles
(without wait state, the divisor being a register).
Interrupt factors
page 56 of 205
Instruction
(a)
Interrupt response time
Interrupt request acknowledged
Interrupt sequence
20 cycles (b)
interrupt routine
Instruction in
Level that is set to IPL
Not changed
7
10.1 Interrupt Overview
Time

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