R5F21133DFP RENESAS [Renesas Technology Corp], R5F21133DFP Datasheet - Page 77

• Manufacturer Part Number: R5F21133DFP
• Description: 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY/R8C/Tiny SERIES
• Manufacturer: RENESAS [Renesas Technology Corp]

R8C/13 Group
Rev.1.20
REJ09B0111-0120
Table 10.7 Relationship Between Address Match Interrupt Sources and Associated Registers
Table 10.6 Value of PC Saved to Stack when Address Match Interrupt Acknowledged
Address match interrupt 0
Address match interrupt 1
10.4 Address Match Interrupt
• 16-bit operation code instruction
• Instruction shown below among 8-bit operation code instructions
• Instructions other than the above
Address match interrupt factors
An address match interrupt is generated immediately before executing the instruction at the address
indicated by the RMADi register (i=0, 1). Set the start address of any instruction in the RMADi register.
Use the AIER0 and AIER1 bits in the AIER register to enable or disable the interrupt. Note that the
address match interrupt is unaffected by the I flag and IPL.
The value of the PC that is saved to the stack when an address match interrupt is acknowledged varies
depending on the instruction at the address indicated by the RMAD i register (see the paragraph “register
saving” for the value of the PC). Not appropriate return address is pushed on the stack. There are two
ways to return from the address match interrupt as follows:
• Change the content of the stack and use a REIT instruction.
• Use an instruction such as POP to restore the stack as it was before an interrupt request was acknowl-
edged. And then use a jump instruction.
Table 10.6 lists the value of the PC that is saved to the stack when an address match interrupt is acknowl-
edged.
Figure 10.17 shows the AIER, and RMAD1 to RMAD0 registers.
ADD.B:S #IMM8,dest
OR.B:S
STNZ.B:S #IMM8,dest
CMP.B:S #IMM8,dest
JMPS
MOV.B:S #IMM,dest (However, dest = A0 or A1)
NOTES:
1. See the paragraph “saving registers” for the PC value saved.
Jan 27, 2006
Address indicated by RMADi register (i=0,1)
#IMM8,dest
#IMM8
page 66 of 205
SUB.B:S #IMM8,dest AND.B:S #IMM8,dest
MOV.B:S #IMM8,dest STZ.B:S #IMM8,dest
STZX.B:S #IMM81,#IMM82,dest
PUSHM
JSRS
Address match interrupt enable bit
AIER0
AIER1
src
#IMM8
POPM dest
RMAD0
RMAD1
Address match interrupt register
10.4 Address Match Interrupt
Address indicated by
RMADi register + 2
Address indicated by
RMADi register + 1
PC value saved
(1)