X4043 INTERSIL [Intersil Corporation], X4043 Datasheet - Page 12

• Manufacturer Part Number: X4043
• Description: CPU Supervisor with 4kbit EEPROM
• Manufacturer: INTERSIL [Intersil Corporation]

Figure 10. Byte Write Sequence
Page Write
The device is capable of a page write operation. It is
initiated in the same manner as the byte write opera-
tion; but instead of terminating the write cycle after the
first data byte is transferred, the master can transmit
an unlimited number of 8-bit bytes. After the receipt of
each byte, the device will respond with an acknowl-
edge, and the address is internally incremented by
one. The page address remains constant. When the
counter reaches the end of the page, it “rolls over” and
Figure 11. Page Write Operation
Figure 12. Writing 12-bytes to a 16-byte page starting at location 10
The master terminates the data byte loading by issu-
ing a stop condition, which causes the device to begin
the nonvolatile write cycle. As with the byte write opera-
tion, all inputs are disabled until completion of the inter-
nal write cycle. See Figure 11 for the address,
acknowledge, and data transfer sequence.
Signals from
Signals from
the Master
the Slave
SDA Bus
7 Bytes
Address
Signals from
Signals from
12
= 6
the Master
the Slave
SDA Bus
S
a
t
r
t
Address
Slave
Address Pointer
Ends Here
Addr = 7
S
a
t
r
t
0
Address
Slave
C
A
K
X4043, X4045
Address
Byte
0
A
C
K
Address
Address
goes back to ‘0’ on the same page. This means that
the master can write 16 bytes to the page starting at
any location on that page. If the master begins writing
at location 10, and loads 12 bytes, then the first 5
bytes are written to locations 10 through 15, and the
last 7 bytes are written to locations 0 through 6. After-
wards, the address counter would point to location 7 of
the page that was just written. If the master supplies
more than 16 bytes of data, then new data over-writes
the previous data, one byte at a time.
Stops and Write Modes
Stop conditions (that terminate write operations) must
be sent by the master after sending at least 1 full data
byte, plus the subsequent ACK signal. If a stop is
issued in the middle of a data byte, or before 1 full
data byte plus its associated ACK is sent, then the
device will reset itself without performing the write. The
contents of the array will not be effected.
Byte
A
C
K
10
Data
(1)
C
A
K
Data
5 Bytes
(1 ≤ n ≤16)
A
C
K
Data
Address
(n)
n-1
A
C
K
S
o
p
t
C
A
K
S
o
p
t
September 30, 2005
FN8118.1