X4043 INTERSIL [Intersil Corporation], X4043 Datasheet - Page 18

• Manufacturer Part Number: X4043
• Description: CPU Supervisor with 4kbit EEPROM
• Manufacturer: INTERSIL [Intersil Corporation]

TIMING DIAGRAMS
Bus Timing
WP Pin Timing
Write Cycle Timing
Nonvolatile Write Cycle Timing
Notes: (7) t
SDA OUT
Symbol
SDA IN
t
WC
SCL
SDA
SCL
the minimum cycle time to be allowed for any nonvolatile write by the user, unless acknowledge polling is used.
(7)
WC
is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is
t
SU:STA
SDA IN
SCL
WP
Write cycle time
8
th
Bit of Last Byte
t
HD:STA
18
START
t
F
t
SU:WP
Parameter
t
SU:DAT
Clk 1
t
HIGH
ACK
X4043, X4045
Slave Address Byte
t
LOW
t
HD:DAT
Condition
Stop
Min.
t
R
t
AA
t
HD:WP
Clk 9
t
WC
Typ.
t
DH
5
(7)
Condition
Start
Max.
t
10
BUF
t
SU:STO
September 30, 2005
Unit
ms
FN8118.1