X4043 INTERSIL [Intersil Corporation], X4043 Datasheet - Page 5

• Manufacturer Part Number: X4043
• Description: CPU Supervisor with 4kbit EEPROM
• Manufacturer: INTERSIL [Intersil Corporation]

PRINCIPLES OF OPERATION
Power-on Reset
Application of power to the X4043/45 activates a
Power-on Reset Circuit that pulls the RESET/RESET
pin active. This signal provides several benefits.
– It prevents the system microprocessor from starting
– It prevents the processor from operating prior to sta-
– It allows time for an FPGA to download its configura-
When V
for
RESET/RESET allowing the system to begin operation.
Low Voltage Monitoring
During operation, the X4043/45 monitors the V
and asserts RESET/RESET if supply voltage falls
below a preset minimum V
signal prevents the microprocessor from operating in a
power fail or brownout condition. The RESET/RESET
signal remains active until the voltage drops below 1V.
It also remains active until V
V
Watchdog Timer
The Watchdog Timer circuit monitors the microproces-
sor activity by monitoring the SDA and SCL pins. A
standard read or write sequence to any slave address
byte restarts the watchdog timer and prevents the
(RESET/RESET) signal going active. A minimum
sequence to reset the watchdog timer requires four
microprocessor intructions namely, a Start, Clock Low,
Clock High and Stop. (See Page 18) The state of two
Figure 2. Set V
TRIP
to operate with insufficient voltage.
bilization of the oscillator.
tion prior to initialization of the circuit.
SDA
SCL
WP
for 200ms.
200ms
CC
exceeds the device V
TRIP
(nominal)
0 1 2 3 4 5 6 7
Level Sequence (V
5
TRIP
A0h
the
CC
. The RESET/RESET
returns and exceeds
TRIP
circuit
threshold value
CC
= desired V
0 1 2 3 4 5 6 7
releases
CC
level
X4043, X4045
V
01h
P
= 15-18V
TRIP
values WEL bit set)
nonvolatile control bits in the status register determine
the watchdog timer period. The microprocessor can
change these watchdog bits, or they may be “locked”
by tying the WP pin HIGH.
Figure 1. Watchdog Restart
EEPROM Inadvertent Write Protection
When RESET/RESET goes active as a result of a low
voltage condition (V
munications are terminated. While V
communications are allowed and no nonvolatile write
operation can start. Nonvolatile writes in-progress when
RESET/RESET goes active are allowed to finish.
Additional protection mechanisms are provided with
memory block lock and the Write Protect (WP) pin.
These are discussed elsewhere in this document.
V
The X4043/45 is shipped with a standard V
old (V
normal operating and storage conditions. However, in
applications where the standard V
right, or if higher precision is needed in the V
value, the X4043/45 threshold may be adjusted. The
procedure is described below, and uses the applica-
tion of a high voltage control signal.
SCL
SDA
TRIP
Programming
TRIP
0 1 2 3 4 5 6 7
) voltage. This value will not change over
Start
.6µs
00h
CC
< V
1.3µs
TRIP
), any in-progress com-
WDT
CC
TRIP
Reset
< V
is not exactly
September 30, 2005
TRIP
CC
Stop
, no new
thresh-
FN8118.1
TRIP