X40431 XICOR [Xicor Inc.], X40431 Datasheet
X40431
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X40431 Summary of contents
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... EEPROM Array Manual Reset + V TRIP1 V Monitor - CC Logic www.xicor.com activates the power on reset CC point. RESET/ TRIP1 returns to proper operating CC V3FAIL V2FAIL Watchdog and WDO Reset Logic MR RESET Power on, X40430 Low Voltage RESET Reset X40431 Generation LOWLINE Characteristics subject to change without notice ...
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... Manual Reset Input. Pulling the MR pin LOW initiates a system reset. The RESET/RESET pin will remain HIGH/LOW until the pin is released and for the t 6 RESET/ RESET Output. (X40431) This open drain pin is an active LOW output which goes LOW whenever V falls below V RESET ...
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... When V exceeds the device V CC for t (selectable) the circuit releases the RESET PURST (X40431) and RESET (X40430) pin allowing the system to begin operation. REV 1.2.3 11/28/00 Function . There is no power up reset delay circuitry on this pin. TRIP3 Figure 1. Connecting a Manual Reset Push-Button ...
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... X40430/X40431 – Preliminary Information Low Voltage V (V1 Monitoring) CC During operation, the X40430 monitors the V and asserts RESET if supply voltage falls below a pre- set minimum V . The RESET signal prevents the TRIP1 microprocessor from operating in a power fail or brownout condition. The RESET/RESET remains active until the voltage drops below 1V. It also ...
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... X40430/X40431 – Preliminary Information Figure 3. V Set/Reset Conditions TRIPX TRIPX WDO 0 SCL SDA A0h WATCHDOG TIMER The Watchdog Timer circuit monitors the microproces- sor activity by monitoring the SDA and SCL pins. The microprocessor must toggle the SDA pin HIGH to LOW ...
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... X40430/X40431 – Preliminary Information Note: This operation does not corrupt the memory array. Setting a Lower V Voltage (x= TRIPx In order to set lower voltage than the TRIPx present value, then V must first be “reset” accord- TRIPx ing to the procedure described below. Once V has been “ ...
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... X40430/X40431 – Preliminary Information Figure 6. V Set/Reset Sequence ( TRIP New V applied = X Old V applied + Error X Error < -MDE WEL: Write Enable Latch (Volatile) The WEL bit controls the access to the memory and to the Register during a write operation. This bit is a vola- tile latch that powers up in the LOW (disabled) state ...
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... X40430/X40431 – Preliminary Information BP1, BP0: Block Protect Bits (Nonvolatile) The Block Protect Bits, BP1 and BP0, determine which blocks of the array are write protected. A write to a pro- tected block of memory is ignored. The block protect bits will prevent write operations to one of eight seg- ments of the array ...
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... X40430/X40431 – Preliminary Information Figure 7. Valid Data Changes on the SDA Bus SCL SDA At power-up, the FDR is defaulted to all “0”. The sys- tem needs to initialize this register to all “1” before the actual monitoring can take place. In the event of any one of the monitored sources fail. The corresponding bit in the register will change from a “ ...
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... X40430/X40431 – Preliminary Information Figure 8. Valid Start and Stop Conditions SCL SDA Serial Acknowledge Acknowledge is a software convention used to indicate successful data transfer. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle, the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data ...
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... X40430/X40431 – Preliminary Information Figure 10. Byte Write Sequence Signals from the Master SDA Bus Signals from the Slave Page Write The device is capable of a page write operation initiated in the same manner as the byte write opera- tion; but instead of terminating the write cycle after the fi ...
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... X40430/X40431 – Preliminary Information Stops and Write Modes Stop conditions that terminate write operations must be sent by the master after sending at least 1 full data byte plus the subsequent ACK signal stop is issued in the middle of a data byte, or before 1 full data byte plus its associated ACK is sent, then the device will reset itself without performing the write ...
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... X40430/X40431 – Preliminary Information A similar operation called “Set Current Address” where the device will perform this operation if a stop is issued instead of the second start shown in Figure 14. The device will go into standby mode after the stop and all bus activity will be ignored until a start is detected. This operation loads the new address into the address counter ...
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... X40430/X40431 – Preliminary Information Word Address The word address is either supplied by the master or obtained from an internal counter. The internal counter is undefined on a power up condition. Operational Notes The device powers-up in the following state: – The device is in the low power standby state. ...
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... X40430/X40431 – Preliminary Information ABSOLUTE MAXIMUM RATINGS Temperature under bias ................... –65°C to +135°C Storage temperature ........................ –65°C to +150°C Voltage on any pin with respect to V ......................................–1.0V to +7V SS D.C. output current ............................................... 5mA Lead temperature (soldering, 10 seconds)........ 300°C RECOMMENDED OPERATING CONDITIONS Temperature Min ...
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... X40430/X40431 – Preliminary Information D.C. OPERATING CHARACTERISTICS (Continued) (Over the recommended operating conditions unless otherwise specified) Symbol Parameter Second Supply Monitor I V2MON Current V2 V V2MON Trip Point Voltage TRIP2 V V2MON Hysteresis V2H Third Supply Monitor I V3MON Current V3 V V3MON Trip Point Voltage ...
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... X40430/X40431 – Preliminary Information A.C. CHARACTERISTICS Symbol f SCL Clock Frequency SCL t Pulse width Suppression Time at inputs IN t SCL LOW to SDA Data Out Valid AA t Time the bus free before start of new transmission BUF t Clock LOW Time LOW t Clock HIGH Time HIGH t Start Condition Setup Time ...
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... X40430/X40431 – Preliminary Information WP Pin Timing START SCL SDA IN t SU:WP WP Write Cycle Timing SCL SDA th 8 Bit of Last Byte Nonvolatile Write Cycle Timing Symbol (1) t Write Cycle Time WC Note: ( the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. ...
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... X40430/X40431 – Preliminary Information RESET/RESET/MR Timings V TRIP1 PURST t R RESET V RVALID RESET MR LOW VOLTAGE AND WATCHDOG TIMINGS PARAMETERS Symbol RESET/RESET (Power down only) RPD1 TRIP1 LOWLINE RPDL TRIP1 t LOWLINE to RESET/RESET delay (Power down only V2FAIL RPDX ...
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... X40430/X40431 – Preliminary Information Watchdog Time Out For 2-Wire Interface Start SCL Timer Start SDA WDO V Set/Reset Conditions TRIPX (V TRIPX t TSU WDO t VPS SCL 0 SDA A0h Start REV 1.2.3 11/28/00 Start t RSP < t WDO Timer Start ) V /V2MON/V3MON 01h* 03h* sets V ...
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... X40430/X40431 – Preliminary Information Programming Specifications: V TRIP1 TRIP2 TRIP3 Parameter t WDO Program Voltage Setup time VPS t WDO Program Voltage Hold time VPH t V Level Setup time TSU TRIPX t V Level Hold (stable) time THD TRIPX t V Program Cycle WC TRIPX t Program Voltage Off time before next cycle ...
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... X40430/X40431 – Preliminary Information PACKAGING INFORMATION 14-Lead Plastic Small Outline Gullwing Package Type S Pin 1 Index Pin 1 0.014 (0.35) 0.020 (0.51) (4X) 7° 0.050 (1.27) 0.010 (0.25) 0.020 (0.50) 0° – 8° 0.016 (0.410) 0.037 (0.937) NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) REV 1.2.3 11/28/00 0.150 (3.80) 0.158 (4.00) 0.336 (8.55) 0.345 (8.75) ...
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... X40430/X40431 – Preliminary Information PACKAGING INFORMATION 0° - 8° See Detail “A” NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) REV 1.2.3 11/28/00 14-Lead Plastic, TSSOP, Package Type V .025 (.65) BSC .169 (4.3) .177 (4.5) .193 (4.9) .200 (5.1) .0075 (.19) .002 (.05) .0118 (.30) .006 (.15) .010 (.25) .019 (.50) .029 (.75) Detail A (20X) www.xicor.com .252 (6.4) BSC ...
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... X40430/X40431 – Preliminary Information ORDERING INFORMATION TRIP1 TRIP2 Range Range Range 2.7-5.5 4.6V±50mV 2.9V±50mV 1.7V±50mV 2.7-5.5 4.4V±50mV 2.6V±50mV 1.7V±50mV 2.4-3.6 2.9V±50mV 1.7V±50mV 2.6V±50mV PART MARK INFORMATION 14-Lead TSSOP EYWW 40430X LIMITED WARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fi ...