X40431 XICOR [Xicor Inc.], X40431 Datasheet - Page 2

• Manufacturer Part Number: X40431
• Description: 4kbit EEPROM, Triple Voltage Monitor with Integrated CPU Supervisor
• Manufacturer: XICOR [Xicor Inc.]

X40430/X40431 – Preliminary Information
A manual reset input provides debounce circuitry for
minimum reset component count.
The Watchdog Timer provides an independent protec-
tion mechanism for microcontrollers. When the micro-
controller fails to restart a timer within a selectable time
out interval, the device activates the WDO signal. The
user selects the interval from three preset values. Once
selected, the interval does not change, even after
cycling the power.
PIN CONFIGURATION
PIN DESCRIPTION
REV 1.2.3 11/28/00
Pin
1
2
3
4
5
6
7
LOWLINE
V2MON
RESET/
V2FAIL
RESET
Name
V
MR
NC
SS
LOWLINE
V2MON
RESET
V2FAIL
V2 Voltage Fail Output. This open drain output goes LOW when V2MON is less than V
goes HIGH when V2MON exceeds V
V2 Voltage Monitor Input. When the V2MON input is less than the V
LOW. This input can monitor an unregulated power supply with an external resistor divider or can
monitor a second power supply with no external components. Connect V2MON to V
when not used.
Early Low V
when
No connect.
Manual Reset Input. Pulling the MR pin LOW initiates a system reset. The RESET/RESET pin will
remain HIGH/LOW until the pin is released and for the t
RESET Output. (X40431) This open drain pin is an active LOW output which goes LOW whenever
V
grammed time period (t
and for t
RESET Output. (X40430) This pin is an active HIGH CMOS output which goes HIGH whenever
V
grammed time period (t
and for t
Ground
V
MR
NC
CC
CC
SS
falls below V
falls below V
14-Pin SOIC, TSSOP
V
1
2
3
4
5
6
7
CC
PURST
PURST
X40430
> V
CC
TRIP1
thereafter.
thereafter.
Detect. This CMOS output signal goes LOW when
TRIP
TRIP
14
13
12
11
10
9
8
.
voltage or if manual reset is asserted. This output stays active for the pro-
voltage or if manual reset is asserted. This output stays active for the pro-
PURST
PURST
V
WDO
V3FAIL
V3MON
WP
SCL
SDA
CC
www.xicor.com
) on power up. It will also stay active until manual reset is released
) on power up. It will also stay active until manual reset is released
TRIP2
The memory portion of the device is a CMOS Serial
EEPROM array with Xicor’s Block Lock protection. The
array is internally organized as x 8. The device features
a 2-wire interface and software protocol allowing opera-
tion on an I
The device utilizes Xicor’s proprietary Direct Write
cell, providing a minimum endurance of 1,000,000
cycles and a minimum data retention of 100 years.
. There is no power up reset delay circuitry on this pin.
Function
LOWLINE
V2MON
V2FAIL
RESET
V
MR
NC
2
SS
C bus.
14-Pin SOIC, TSSOP
PURST
1
2
3
4
5
6
7
Characteristics subject to change without notice.
X40431
thereafter.
V
14
13
12
11
10
TRIP2
CC
9
8
< V
V
WDO
V3FAIL
V3MON
WP
SCL
SDA
voltage, V2FAIL goes
CC
TRIP1
and goes high
SS
TRIP2
or
V
CC
2 of 24
and
™