WM8980CGEFL/RV WOLFSON [Wolfson Microelectronics plc], WM8980CGEFL/RV Datasheet - Page 31

• Manufacturer Part Number: WM8980CGEFL/RV
• Description: Stereo CODEC with Speaker Driver and Video Buffer
• Manufacturer: WOLFSON [Wolfson Microelectronics plc]

Pre-Production
ANALOGUE TO DIGITAL CONVERTER (ADC)
Figure 16 ADC Digital Filter Path
w
ADC DIGITAL FILTERS
Table 12 ADC Enable Control
Table 13 ADC Control
The WM8980 uses stereo multi-bit, oversampled sigma-delta ADCs. The use of multi-bit feedback
and high oversampling rates reduces the effects of jitter and high frequency noise. The ADC Full
Scale input level is proportional to AVDD. With a 3.3V supply voltage, the full scale level is 1.0V
Any voltage greater than full scale may overload the ADC and cause distortion.
The ADC filters perform true 24 bit signal processing to convert the raw multi-bit oversampled data
from the ADC to the correct sampling frequency to be output on the digital audio interface. The digital
filter path for each ADC channel is illustrated in Figure 16.
The ADCs are enabled by the ADCENL/R register bit.
The polarity of the output signal can also be changed under software control using the
ADCLPOL/ADCRPOL register bit. The oversampling rate of the ADC can be adjusted using the
ADCOSR register bit. With ADCOSR=0 the oversample rate is 64x which gives lowest power
operation and when ADCOSR=1 the oversample rate is 128x which gives best performance.
R2
Power
management 2
R14
ADC Control
REGISTER
REGISTER
ADDRESS
ADDRESS
0
1
0
1
3
BIT
BIT
ADCENL
ADCENR
ADCLPOL
ADCRPOL
ADCOSR
LABEL
LABEL
0
0
DEFAULT
0
0
0
DEFAULT
Enable ADC left channel:
0 = ADC disabled
1 = ADC enabled
Enable ADC right channel:
0 = ADC disabled
1 = ADC enabled
ADC left channel polarity adjust:
0=normal
1=inverted
ADC right channel polarity adjust:
0=normal
1=inverted
ADC oversample rate select:
0=64x (lower power)
1=128x (best performance)
DESCRIPTION
DESCRIPTION
PP, Rev 3.8, May 2012
WM8980
rms
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