WM8980CGEFL/RV WOLFSON [Wolfson Microelectronics plc], WM8980CGEFL/RV Datasheet - Page 82

• Manufacturer Part Number: WM8980CGEFL/RV
• Description: Stereo CODEC with Speaker Driver and Video Buffer
• Manufacturer: WOLFSON [Wolfson Microelectronics plc]

WM8980
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Table 61 Companding Control
Table 62 8-bit Companded Word Composition
Companding involves using a piecewise linear approximation of the following equations (as set out
by ITU-T G.711 standard) for data compression:
-law (where =255 for the U.S. and Japan):
F(x) = ln( 1 + |x|) / ln( 1 + )
A-law (where A=87.6 for Europe):
F(x) = A|x| / ( 1 + lnA)
F(x) = ( 1 + lnA|x|) / (1 + lnA)
The companded data is also inverted as recommended by the G.711 standard (all 8 bits are inverted
for -law, all even data bits are inverted for A-law). The data will be transmitted as the first 8 MSB’s
of data.
Companding converts 13 bits (-law) or 12 bits (A-law) to 8 bits using non-linear quantization. The
input data range is separated into 8 levels, allowing low amplitude signals better precision than that
of high amplitude signals. This is to exploit the operation of the human auditory system, where louder
sounds do not require as much resolution as quieter sounds. The companded signal is an 8-bit word
containing sign (1-bit), exponent (3-bits) and mantissa (4-bits).
Setting the WL8 register bit allows the device to operate with 8-bit data. In this mode it is possible to
use 8 BCLK’s per LRC frame. When using DSP mode B, this allows 8-bit data words to be output
consecutively every 8 BCLK’s and can be used with 8-bit data words using the A-law and u-law
companding functions.
R5
Companding
Control
SIGN
BIT7
REGISTER
ADDRESS
0
2:1
4:3
5
BIT
EXPONENT
BIT[6:4]
LOOPBACK
ADC_COMP
DAC_COMP
WL8
LABEL
-1 ≤ x ≤ 1
 for x ≤ 1/A
 for 1/A ≤ x ≤ 1
0
0
0
0
DEFAULT
Digital loopback function
0=No loopback
1=Loopback enabled, ADC data output
is fed directly into DAC data input.
ADC companding
00=off (linear mode)
01=reserved
10=µ-law
11=A-law
DAC companding
00=off (linear mode)
01=reserved
10=µ-law
11=A-law
Companding Control 8-bit mode
0=off
1=device operates in 8-bit mode
MANTISSA
BIT[3:0]
DESCRIPTION
PP, Rev 3.8, May 2012
Pre-Production
82