WM8980CGEFL/RV WOLFSON [Wolfson Microelectronics plc], WM8980CGEFL/RV Datasheet - Page 98

• Manufacturer Part Number: WM8980CGEFL/RV
• Description: Stereo CODEC with Speaker Driver and Video Buffer
• Manufacturer: WOLFSON [Wolfson Microelectronics plc]

WM8980
w
6 (06h)
7 (07h)
8 (08h)
REGISTER
ADDRESS
8
7:5
4:2
1
0
8:4
3:1
0
8:6
5:4
3
BIT
CLKSEL
MCLKDIV
BCLKDIV
MS
SR
SLOWCLKEN
OPCLKDIV
GPIO1POL
LABEL
1
010
000
0
0
00000
000
0
000
00
0
DEFAULT
Controls the source of the clock for all internal
operation:
0=MCLK
1=PLL output
Sets the scaling for either the MCLK or PLL clock
output (under control of CLKSEL)
000=divide by 1
001=divide by 1.5
010=divide by 2
011=divide by 3
100=divide by 4
101=divide by 6
110=divide by 8
111=divide by 12
Configures the BCLK output frequency, for use
when the chip is master over BCLK.
000=divide by 1 (BCLK=SYSCLK)
001=divide by 2 (BCLK=SYSCLK/2)
010=divide by 4
011=divide by 8
100=divide by 16
101=divide by 32
110=reserved
111=reserved
Reserved
Sets the chip to be master over LRC and BCLK
0=BCLK and LRC clock are inputs
1=BCLK and LRC clock are outputs generated by
the WM8980 (MASTER)
Reserved
Approximate sample rate (configures the
coefficients for the internal digital filters):
000=48kHz
001=32kHz
010=24kHz
011=16kHz
100=12kHz
101=8kHz
110-111=reserved
Slow clock enable. Used for both the jack insert
detect debounce circuit and the zero cross
timeout.
0 = slow clock disabled
1 = slow clock enabled
Reserved
PLL Output clock division ratio
00=divide by 1
01=divide by 2
10=divide by 3
11=divide by 4
GPIO1 Polarity invert
0=Non inverted
1=Inverted
DESCRIPTION
PP, Rev 3.8, May 2012
Digital Audio
Interfaces
Digital Audio
Interfaces
Digital Audio
Interfaces
Digital Audio
Interfaces
Audio Sample
Rates
Analogue
Outputs
General
Purpose
Input/Output
(GPIO)
General
Purpose
Input/Output
(GPIO)
REFER TO
Pre-Production
98