WM8980CGEFL/RV WOLFSON [Wolfson Microelectronics plc], WM8980CGEFL/RV Datasheet - Page 80

• Manufacturer Part Number: WM8980CGEFL/RV
• Description: Stereo CODEC with Speaker Driver and Video Buffer
• Manufacturer: WOLFSON [Wolfson Microelectronics plc]

WM8980
Figure 48 PLL and Clock Select Circuit
w
EXAMPLE:
MCLK=12MHz, required clock = 12.288MHz.
R should be chosen to ensure 5 < PLLN < 13. There is a fixed divide by 4 in the PLL and a selectable
divide by N after the PLL which should be set to divide by 2 to meet this requirement.
Enabling the divide by 2 sets the required f
Table 59 PLL Frequency Ratio Control
The PLL frequency ratio R = f
Note: The PLL is designed to operate with best performance (shortest lock time and optimum
stability) when f
in the range 5 ≤ PLL_N ≤ 13. Do not use values outwith this range and it is recommended that the
chosen value of PLL_N is as close to 8 as possible for optimum performance.
R36
PLL N value
R37
PLL K value
1
R38
PLL K Value
2
R39
PLL K Value
3
REGISTER
ADDRESS
PLLN = int R
PLLK = int (2
R = 98.304 / 12 = 8.192
PLLN = int R = 8
k = int ( 2
2
is between 90 and 100MHz and PLL_N is 8. However, acceptable PLL_N values lie
4
3:0
5:0
8:0
8:0
BIT
24
x (8.192 – 8)) = 3221225 = 3126E9h
24
PLLPRESCALE
PLLN[3:0]
PLLK [23:18]
PLLK [17:9]
PLLK [8:0]
(R-PLLN))
2
/f
1
LABEL
(see Figure 48) can be set using the register bits PLLK and PLLN:
2
= 4 x 2 x 12.288MHz = 98.304MHz.
0
1000
0Ch
093h
0E9h
DEFAULT
Divide MCLK by 2 before input to
PLL
Integer (N) part of PLL input/output
frequency ratio. Use values greater
than 5 and less than 13.
Fractional (K) part of PLL1
input/output frequency ratio (treat as
one 24-digit binary number).
DESCRIPTION
PP, Rev 3.8, May 2012
Pre-Production
80