WM9712CLGEFL/RV WOLFSON [Wolfson Microelectronics plc], WM9712CLGEFL/RV Datasheet - Page 59

• Manufacturer Part Number: WM9712CLGEFL/RV
• Manufacturer: WOLFSON [Wolfson Microelectronics plc]

Production Data
w
INTERFACE TIMING
Test Characteristics:
DBVDD = 3.3V, DCVDD = 3.3V, DGND1 = DGND2 = 0V, T
CLOCK SPECIFICATIONS
Figure 17 Clock Specifications (50pF External Load)
DATA SETUP AND HOLD
Figure 18 Data Setup and Hold (50pF External Load)
Note:
Setup and hold times for SDATAIN are with respect to the AC’97 controller, not the WM9712L.
Note:
1. Worst case duty cycle restricted to 45/55
PARAMETER
BITCLK frequency
BITCLK period
BITCLK output jitter
BITCLK high pulse width (Note 1)
BITCLK low pulse width (Note 1)
SYNC frequency
SYNC period
SYNC high pulse width
SYNC low pulse width
PARAMETER
Setup to falling edge of BITCLK
Hold from falling edge of BITCLK
Output valid delay from rising edge of
BITCLK
BITCLK
SYNC
t
SYNC_HIGH
A
t
= -25C to +85C, unless otherwise stated.
CLK_PERIOD
t
CLK_HIGH
SYMBOL
SYMBOL
t
t
SYNC_PERIOD
t
t
CLK_PERIOD
t
SYNC_HIGH
t
SYNC_LOW
CLK_HIGH
t
CLK_LOW
t
SYNC_PERIOD
t
SETUP
HOLD
t
CO
t
CLK_LOW
t
SYNC_LOW
MIN
MIN
36
36
10
10
TYP
TYP
PD, Rev 4.6, November 2011
12.288
81.4
40.7
40.7
20.8
19.5
1.3
48
MAX
MAX
750
WM9712L
45
45
15
UNIT
UNIT
MHz
kHz
ns
ps
ns
ns
s
s
s
ns
ns
ns
59