WM9712CLGEFL/RV WOLFSON [Wolfson Microelectronics plc], WM9712CLGEFL/RV Datasheet - Page 61

• Manufacturer Part Number: WM9712CLGEFL/RV
• Manufacturer: WOLFSON [Wolfson Microelectronics plc]

Production Data
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COLD RESET (ASYNCHRONOUS, RESETS REGISTER SETTINGS)
Figure 21 Cold Reset Timing
Note:
For correct operation SDATAOUT and SYNC must be held LOW for entire RESETB active
low period otherwise the device may enter test mode. See AC'97 specification or Wolfson
applications note WAN104 for more details.
WARM RESET (ASYNCHRONOUS, PRESERVES REGISTER SETTINGS)
Figure 22 Warm Reset Timing
PARAMETER
RESETB active low pulse width
RESETB inactive to BITCLK startup
delay
PARAMETER
SYNC active high pulse width
SYNC inactive to BITCLK startup
delay
RESETB
BITCLK
t
RST_LOW
SYMBOL
SYMBOL
t
t
SYNC_HIGH
t
t
RST_LOW
RST2CLK
RST2CLK
t
RST2CLK
MIN
MIN
162.8
162.4
1.0
TYP
TYP
PD, Rev 4.6, November 2011
1.3
MAX
MAX
WM9712L
UNIT
UNIT
s
ns
s
ns
61